Design Engineer Lead

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    "datePosted": "2026-02-10T05:00:00.000Z",
    "description": "<h2>Lattice Overview</h2>\n<p>There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.</p>\n<h2>Responsibilities & Skills</h2>\n<p><strong>Job Requirements:</strong></p>\n<ul>\n <li>20yrs experience of hardware IP and integration design</li>\n <li>Led a team of cross-functional engineers across multiple sites/geos</li>\n <li>Led multiple programs from concept to Tape Out and production release</li>\n <li>Expertise in System Verilog, Synthesis, and Static Timing Analysis</li>\n <li>Good understanding of DFx (test and debug) methodology on IP and chip level</li>\n <li>Ability to debug complex issues with floor-planning, power distribution network, system level clocking, timing closure and SIPI</li>\n <li>Deep experience in one or more of following domains: High speed interfaces (LPDDR5, USB4.0, Chip-to-Chip interconnects), System Interconnects (Coherent NoC, AMBA), processors (ARM, MIPS, RISC-V) and FPGA systems</li>\n <li>Experience debugging complex system level use cases through verification, emulation and system validation</li>\n <li>Programming skills (e.g.: C/C++, Perl, TCL or Python) and proficient in using GenAI and agentic AI methodologies for scaling design</li>\n <li>Strong written and oral communication skills. Frequent presentations to executive leadership on status of projects and roadmaps</li>\n <li>Ability to drive IP roadmap with deep engagement with leading IP vendors and execute competitive analysis and benchmarking</li>\n <li>The ability to stay on top of latest advancements in technology, design and AI</li>\n</ul>\n<h2>Benefits</h2>\n<p><strong>Benefits:</strong>The base pay for this role is between $175,000 to $219,000 per year. In addition to base salary, we offer an incentive plan bonus, and new hire equity for a competitive total compensation package. Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. </p>\n<p>Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.</p>\n<p> </p>\n<p>LatticeFeel the energy.</p>",
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