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HomeCompaniesSamsung SemiconductorPrincipal Engineer, SOC Design

Principal Engineer, SOC Design

Samsung Semiconductor · San Jose, California, United States · On Site · Active · $219,000–$351,000 / year · Greenhouse

Job facts

FieldValue
CompanySamsung Semiconductor
TitlePrincipal Engineer, SOC Design
Normalized title-
Department / teamDRAM Design Lab (DDL)
LocationSan Jose, CA, United States
Work modelOn Site
Employment typeFull Time
Salary$219,000–$351,000 / year
Statusactive
ATS providerGreenhouse
Posted / first seen2026-02-23 / 2026-05-29
Changed / last seen2026-06-06 / 2026-06-06

Related slices

PageWhat it containsOpen
Company jobsActive postings from Samsung Semiconductor.Open
Company breakdownsRole, location, ATS, and work model facets for this company.Open
ATS provider jobsActive postings observed through Greenhouse.Open
Provider filtered searchThe same provider as a filtered job collection.Open
City jobsActive postings in San Jose.Open
Department jobsActive postings in DRAM Design Lab (DDL).Open
Work model jobsActive On Site postings.Open
Lifecycle eventsOpen, update, close, and reopen events for this posting.Open
Original postingCanonical source or apply URL captured from the ATS.Open

Linked records

CompanySamsung Semiconductor
Sourcea77fca0e-ff87-493b-8172-e7a20dd1d0d0
ATS providerGreenhouse

Description

Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World’s Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities. Principal Engineer, SOC Design What You’ll Do The DRAM Development Lab (DDL) is part of Samsung’s Memory Business Unit, the industry's technology and volume leader in DRAM, HBM and NAND Flash. DDL’s vision is to solve key problems of Cloud & Data center by developing the new technology for memory and storage. The SOC team within DDL focuses on the development of silicon solutions. We are an integral part of Samsung’s strong R&D focus & lab innovation engine. We work closely with development teams to bring feature innovation to product roadmaps. Come join the team that is creating new computing system architectures needed to support emerging machine learning applications, data analytics and edge computing. You’ll focus on enhancement of memory and storage capability by developing prototype and production controllers. Job ID: 42866 Location: Daily onsite presence at our San Jose or Folsom office in alignment with our Flexible Work policy Participate in architectural definitions and responsible for micro architecture of subsystem and/or chip level. Responsible for top integration, logic design and RTL implementation along with quality check (Assertion, Lint, CDC, and STA). Reviews 3 rd party IPs including ARM cores, DDR controller, and UCIe PHY Responsible for integrating the third part IPs and sub system at top level Work closely with architects and verification engineers to ensure sound design at SoC level. Work with physical designers on timing constraints, synthesis, DFT insertion, and static timing analysis What You Bring Bachelors in Electrical, Computer Science or related with 20+ years of experience or Masters in Electrical, Computer Science or related Science with 18+ years of Industry Experience or PhD in Electrical, Computer Science or related Science with 15+ years of Industry experience preferred. Highly motivated with good verbal and written communication skills. Hands on knowledge & experience in ASIC design flow from design to tape out. Experience & Good knowledge in ATE vector generation, testing and silicon bring up. Experience in the commercial IPs such as UCIe, CPU, Ethernet, and DDR interfaces. Good understanding of PPA (performance, power, and area) trade-offs. Experience in SoC level synthesis, timing analysis, lint check, CDC checks. Experience in interfacing 3 rd party service companies for DFT/PI/PD. Good knowledge and experience in AMBA bus fabric, ARM cores. Self-motivated problem-solver with an ability to work well in a team. You’re inclusive, adapting your style to the situation and diverse global norms of our people. An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. Innovative and creative, you proactively explore new ideas and adapt quickly to change. #LI-SF1 What We Offer The pay range below is for all roles at this level across all US locations and functions. Pay within this range varies by work location and may also depend on job-related knowledge, skills, and experience. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours. Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community. Enjoy Time Away You’ll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge. Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies. Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you’ll have support no matter where you are. Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier. Embrace Flexibility Benefits are best when you have the space to use them. That’s why we facilitate a flexible environment so you can find the right balance for you. Base Pay Range $219,000 — $351,000 USD Equal Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations. Our Commitment to Innovation and Fairness At Samsung Semiconductor, we use Artificial Intelligence (AI) tools in the recruitment process to enhance efficiency. However, AI is used as a support tool, not a final decision-maker. All hiring decisions are made by our human recruiting team and hiring managers to ensure every candidate is evaluated fairly and holistically. Recruiting Agency Policy We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings. Applicant AI Use Policy At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we prohibit the use of generative AI tools to misrepresent a candidate's true skills and qualifications. Permitted uses are limited to basic preparation, grammar, and research, but all submitted content and interview responses must reflect the candidate’s genuine abilities and experience. Violation of this policy may result in immediate disqualification from the hiring process. Trade Secret Notice By submitting an application, you agree not to disclose to Samsung—or encourage Samsung to use—any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity. Applicant Privacy Policy https://semiconductor.samsung.com/about-us/careers/us/privacy/

Full job record

Job ID6bda1192501bb433dd2122e1aaec3067210c4b8a
Org IDccbd8150-365f-4c42-8801-c44fed8e7d0e
Source IDa77fca0e-ff87-493b-8172-e7a20dd1d0d0
Board IDa77fca0e-ff87-493b-8172-e7a20dd1d0d0
Providergreenhouse
Provider Job Key7632691003
TitlePrincipal Engineer, SOC Design
Normalized Title
Statusactive
Activeyes
Location TextSan Jose, California, United States
DepartmentDRAM Design Lab (DDL)
Team
Employment TypeFull-time
Workplace Typeon_site
Remote Policy
CountryUnited States
RegionCA
CitySan Jose
Salary RawBase Pay Range $219,000 — $351,000 USD Equal Opportunity Employment Policy Samsung Semiconductor
Salary Min219,000
Salary Max351,000
Salary CurrencyUSD
Salary Periodyear
Source URLhttps://job-boards.greenhouse.io/samsungsemiconductor/jobs/7632691003
Apply URLhttps://job-boards.greenhouse.io/samsungsemiconductor/jobs/7632691003
First Seen At2026-05-29 23:01:57Z
Last Seen At2026-06-06 07:34:25Z
Last Checked At2026-06-06 07:34:25Z
Last Changed At2026-06-06 07:34:25Z
Inactive At
Source Posted At2026-02-23 21:41:23Z
Source Updated At2026-06-04 17:27:05Z
Raw Payload Uris3://job-postings-prod-raw-590183727216/raw/provider=greenhouse/board=samsungsemiconductor/date=2026-06-06/2026-06-06T07-34-24-838Z-2f6d604392e6fb5d6869c08438985908a9ac6ee923cb947d67f06f5bb441446a.json
Event Fields
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Parsed Structured
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  "salary_period": "year",
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Extensions
{}
Native Structured
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