ASIC Architect

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    "description": "<p><span style=\"font-weight: bold\">About the Role</span></p>\n<p>We are seeking an experienced candidate to lead the miniaturisation of our cutting-edge probabilistic computing platform. This role is pivotal in defining and executing the ASIC strategy, ensuring optimal integration with other processing units such as FPGAs and GPUs. You will work closely with hardware engineers, algorithm designers, and fabrication partners to deliver a high-performance, cost-effective solution.</p>\n<p><br></p>\n<p>We welcome all qualified international candidates to apply for this role. We have offices in Oxford and London, and are open to other international locations. </p>\n<p><br></p>\n<p><span style=\"font-weight: bold\">Key Responsibilities</span></p>\n<ul>\n<li>ASIC strategy &amp; architecture\n<ul>\n<li><span style=\"font-size: 12pt\">Assess system components to determine which should be implemented as ASIC </span><span style=\"font-size: 12pt\">versus FPGA or GPU.</span></li>\n<li><span style=\"font-size: 12pt\">Define ASIC architecture in alignment with overall system requirements, including </span><span style=\"font-size: 12pt\">interfaces and memory hierarchy.</span></li>\n<li><span style=\"font-size: 12pt\">Evaluate trade-offs between different processing units (ASIC, FPGA, GPU, SoC) for </span><span style=\"font-size: 12pt\">performance, power, and scalability.</span></li>\n</ul>\n</li>\n<li>Architectural planning\n<ul>\n<li><span style=\"font-size: 12pt\">Define and own high-level system architecture, refining requirements into </span><span style=\"font-size: 12pt\">functional, logical, and physical architectures, interfaces and constraints</span></li>\n<li><span style=\"font-size: 12pt\">Lead partitioning decisions (analogue vs. digital domain, as well as core compute, </span><span style=\"font-size: 12pt\">memory and IO subsystems, chiplet selection, placement and interconnect </span><span style=\"font-size: 12pt\">strategy)</span></li>\n<li><span style=\"font-size: 12pt\">Oversee internal and third-party IP for design blocks, chiplets, PDKs, chip-to-chip </span><span style=\"font-size: 12pt\">and die-to-die interfaces</span></li>\n<li><span style=\"font-size: 12pt\">Drive top-level floor planning</span></li>\n<li><span style=\"font-size: 12pt\">Direct functional simulations and co-simulation across multiple domains</span></li>\n</ul>\n</li>\n<li>Design &amp; development\n<ul>\n<li><span style=\"font-size: 12pt\">Oversee ASIC design lifecycle: specification, RTL design, verification, and physical </span><span style=\"font-size: 12pt\">implementation.</span></li>\n<li><span style=\"font-size: 12pt\">Ensure compatibility with system-level interfaces and integration requirements.</span></li>\n</ul>\n</li>\n<li>Fabrication &amp; packaging\n<ul>\n<li><span style=\"font-size: 12pt\">Manage relationships with semiconductor foundries and packaging vendors.</span></li>\n<li><span style=\"font-size: 12pt\">Coordinate fabrication, packaging, and testing processes to meet performance </span><span style=\"font-size: 12pt\">and reliability targets.</span></li>\n</ul>\n</li>\n<li>Integration &amp; validation\n<ul>\n<li><span style=\"font-size: 12pt\">Lead integration of ASIC components into the broader computing platform.</span></li>\n<li><span style=\"font-size: 12pt\">Collaborate with software and hardware teams to validate functionality and </span><span style=\"font-size: 12pt\">optimise performance.</span></li>\n</ul>\n</li>\n<li><span style=\"font-size: 12pt\">Project management</span>\n<ul>\n<li><span style=\"font-size: 12pt\">Define milestones, budgets, and resource allocation for the ASIC workstream.</span></li>\n<li><span style=\"font-size: 12pt\">Report progress and risks to senior leadership.</span></li>\n</ul>\n</li>\n</ul>\n<p><br></p>\n<p><span style=\"font-weight: bold\">Required qualifications</span></p>\n<ul>\n<li>Technical expertise\n<ul>\n<li><span style=\"font-size: 12pt\">Strong understanding of system architecture, memory requirements, and </span><span style=\"font-size: 12pt\">interface protocols.</span></li>\n<li><span style=\"font-size: 12pt\">Knowledge of ASIC design flow, including synthesis, place-and-route, and </span><span style=\"font-size: 12pt\">verification.</span></li>\n<li><span style=\"font-size: 12pt\">Familiarity with FPGA and GPU architectures and their respective advantages.</span></li>\n</ul>\n</li>\n<li>Experience\n<ul>\n<li><span style=\"font-size: 12pt\">Proven track record managing ASIC projects from concept to production, </span><span style=\"font-size: 12pt\">including fabrication and packaging.</span></li>\n<li><span style=\"font-size: 12pt\">Experience in heterogeneous computing systems and hardware-software co-</span><span style=\"font-size: 12pt\">design.</span></li>\n</ul>\n</li>\n<li><span style=\"font-size: 12pt\">Skills</span>\n<ul>\n<li><span style=\"font-size: 12pt\">Ability to assess trade-offs between ASIC, FPGA, and GPU implementations.</span></li>\n<li><span style=\"font-size: 12pt\">Excellent communication and leadership skills for cross-functional collaboration.</span></li>\n</ul>\n</li>\n</ul>\n<p><br></p>\n<p><span style=\"font-weight: bold\">Preferred qualifications</span></p>\n<ul>\n<li>Experience with probabilistic or unconventional computing architectures.</li>\n<li><span style=\"font-size: 12pt\">Familiarity with advanced packaging technologies (e.g., chiplets, 2.5D/3D integration).</span></li>\n<li><span style=\"font-size: 12pt\">Knowledge of low-power design techniques and high-speed interfaces.</span></li>\n</ul>\n<p><br></p>\n<p><span style=\"font-weight: bold\">Why Join Us?</span></p>\n<p>You’ll be at the forefront of next-generation computing, shaping a platform that redefines performance and efficiency. This is an opportunity to lead innovation in a rapidly evolving field.</p>",
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