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Packaging and Assembly lead

Lyte AI · Sunnyvale, CA, United States · On Site · Active · $100,000–$200,000 / year · Rippling ATS

Job facts

FieldValue
CompanyLyte AI
TitlePackaging and Assembly lead
Normalized title-
Department / teamOperations
LocationSunnyvale, CA, United States
Work modelOn Site
Employment typeFull Time
Salary$100,000–$200,000 / year
Statusactive
ATS providerRippling ATS
Posted / first seen2026-01-04 / 2026-05-29
Changed / last seen2026-06-06 / 2026-06-06

Related slices

PageWhat it containsOpen
Company jobsActive postings from Lyte AI.Open
Company breakdownsRole, location, ATS, and work model facets for this company.Open
ATS provider jobsActive postings observed through Rippling ATS.Open
Provider filtered searchThe same provider as a filtered job collection.Open
City jobsActive postings in Sunnyvale.Open
Department jobsActive postings in Operations.Open
Work model jobsActive On Site postings.Open
Lifecycle eventsOpen, update, close, and reopen events for this posting.Open
Original postingCanonical source or apply URL captured from the ATS.Open

Linked records

CompanyLyte AI
Sourcef4afde55-a55c-4387-8736-a15d6734cb06
ATS providerRippling ATS

Description

company About Lyte Lyte builds perception systems for Physical AI operating in complex environments. The company combines custom silicon, integrated sensors, and software into a unified platform for robotics, mobility, and next-generation automation. Lyte is headquartered in Sunnyvale, California, with a global presence. For more information, visit www.lyte.ai If you’re excited about building impactful technology in a dynamic, hands-on environment, we’d love to hear from you! role About the role We are seeking an experienced process lead/Manager in the field of optical sensor device packaging and contract manufacture with a degree in Electrical Engineering, Photonics, Mechanical Engineering, Physics or a related field. Describe the role and team the candidate will be joining What you'll do Lead NPI process team involving wafer, device packaging, PCBA assembly process improvement and optimization for yield improvement through material selection optimization, process refinement, or specs opening through DOE for corner case studies. Communicate with the RnD team to understand the design targets, existing specs, and existing process flow, process maturity, and its related yield for each process step. Lead the tradeoff between the design and process. Work with our wafer foundries and OSATs to support NPI and volume production contract manufacture. Lead process integration check to ensure the upstream process will not affect the downstream process yield. Act as the technical program manager for operation process team. Provide DFM, DFR, DFT inputs for HQ RnD teams for device tapeout design ad device packaging during the design phase. Develop and maintain packaging and component specifications as well as inventory tracking. Audit/regularly visit our contract Manufacturers and suppliers then provide reports. Write technical reports and present results to internal and external stakeholders. Build and grow the Operation Process Team worldwide. Write technical SOW. Drive Cp, Cpk, and yield improvement. Required Qualifications Minimal requirement is a Master or Ph.D. degree with 8 years of relevant experience. Experience with process integration for process flow design and continue process improvement. Former experience of microelectronic and optical devices packaging is a must. Project management capability/experience is a must. Experience working with foundries, OSATs, PCBA fab, and contract manufacturers in process development and yield improvement is important. Experience with FMEA, failure analysis, and 8D report. Ability to work independently and take ownership of projects as well as collaboratively in cross-functional teams is a must. Fast learner is a must. Good work ethics is a must Capable of keeping company confidential information and IP is a must. Preferred Qualifications Experience on process flow design, and SPC, particularly the six sigma and Lean manufacture continuing improvement plan, and material staging concept are highly desirable. Familiar with data analysis software such as JMPs is a plus. Knowledge of wafer level process including lithography, thin film, plating, and DIE/DRIE is a plus. Experience with PCBA process is highly desirable. Understanding Silicon Photonics is a plus. Experience in IIIV wafer process, bar level process, and CoC packaging is a plus. Supplier quality management experience is a plus. Knowledge of Lidar and relevant technologies is a plus. Former experience of writing technical SoW is a plus. Familiar with ECN, PCN and documentation are highly desirable. Benefits Competitive salary and equity Comprehensive medical, dental, and vision coverage 401(k) retirement plan Flexible vacation and time-off policy Collaborative, fast-paced, and inclusive work environment Opportunity to work on cutting-edge technologies with a highly cross-functional team

Full job record

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Org ID3c5bf59d-998c-4877-a152-62bdeba1ec4a
Source IDf4afde55-a55c-4387-8736-a15d6734cb06
Board IDf4afde55-a55c-4387-8736-a15d6734cb06
Providerrippling
Provider Job Key29ad1382-434b-489f-a0a1-29ea9e92ae35
TitlePackaging and Assembly lead
Normalized Title
Statusactive
Activeyes
Location TextSunnyvale, CA, United States
DepartmentOperations
Team
Employment Typefull_time
Workplace Typeon_site
Remote Policy
CountryUnited States
RegionCA
CitySunnyvale
Salary RawUSD 100000-200000 YEAR
Salary Min100,000
Salary Max200,000
Salary CurrencyUSD
Salary Periodyear
Source URLhttps://ats.rippling.com/lyte/jobs/29ad1382-434b-489f-a0a1-29ea9e92ae35
Apply URLhttps://ats.rippling.com/lyte/jobs/29ad1382-434b-489f-a0a1-29ea9e92ae35
First Seen At2026-05-29 07:16:45Z
Last Seen At2026-06-06 08:47:06Z
Last Checked At2026-06-06 08:47:06Z
Last Changed At2026-06-06 08:47:06Z
Inactive At
Source Posted At2026-01-04 00:50:12Z
Source Updated At
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      "role": "<meta><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><b><strong style=\"font-size:18pt;white-space:pre-wrap;\">About the role</strong></b></p><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">We are seeking an experienced process lead/Manager in the field of optical sensor device packaging and contract manufacture with a degree in Electrical Engineering, Photonics, Mechanical Engineering, Physics or a related field.</span><span style=\"white-space:pre-wrap;\">Describe the role and team the candidate will be joining</span></li></ul><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><b><strong style=\"font-size:18pt;white-space:pre-wrap;\">What you'll do</strong></b></p><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Lead NPI process team involving wafer, device packaging, PCBA assembly process improvement and optimization for yield improvement through material selection optimization, process refinement, or specs opening through DOE for corner case studies.</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Communicate with the RnD team to understand the design targets, existing specs, and existing process flow, process maturity, and its related yield for each process step.</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Lead the tradeoff between the design and process.</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Work with our wafer foundries and OSATs to support NPI and volume production contract manufacture.</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Lead process integration check to ensure the upstream process will not affect the downstream process yield.</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Act as the technical program manager for operation process team.</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Provide DFM, DFR, DFT inputs for HQ RnD teams for device tapeout design ad device packaging during the design phase.</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Develop and maintain packaging and component specifications as well as inventory tracking.</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Audit/regularly visit our contract Manufacturers and suppliers then provide reports.</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Write technical reports and present results to internal and external stakeholders.</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Build and grow the Operation Process Team worldwide.</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Write technical SOW.</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Drive Cp, Cpk, and yield improvement.</span></li></ul><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><b><strong style=\"font-size:18pt;white-space:pre-wrap;\">Required Qualifications</strong></b></p><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Minimal requirement is a Master or Ph.D. degree with 8 years of relevant experience.</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Experience with process integration for process flow design and continue process improvement.</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Former experience of microelectronic and optical devices packaging is a must.</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Project management capability/experience is a must.</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Experience working with foundries, OSATs, PCBA fab, and contract manufacturers in process development and yield improvement is important.</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Experience with FMEA, failure analysis, and 8D report.</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Ability to work independently and take ownership of projects as well as collaboratively in cross-functional teams is a must.</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Fast learner is a must.</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Good work ethics is a must</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Capable of keeping company confidential information and IP is a must.</span></li></ul><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><b><strong style=\"font-size:18pt;white-space:pre-wrap;\">Preferred Qualifications</strong></b></p><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Experience on process flow design, and SPC, particularly the six sigma and Lean manufacture continuing improvement plan, and material staging concept are highly desirable. </span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Familiar with data analysis software such as JMPs is a plus.</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Knowledge of wafer level process including lithography, thin film, plating, and DIE/DRIE is a plus. </span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Experience with PCBA process is highly desirable.</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Understanding Silicon Photonics is a plus.</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Experience in IIIV wafer process, bar level process, and CoC packaging is a plus. </span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Supplier quality management experience is a plus.</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Knowledge of Lidar and relevant technologies is a plus.</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Former experience of writing technical SoW is a plus.</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Familiar with ECN, PCN and documentation are highly desirable.</span></li></ul><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;text-align:left;\"><b><strong style=\"font-size:18pt;white-space:pre-wrap;\">Benefits</strong></b></p><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:left;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Competitive salary and equity&nbsp;</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:left;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Comprehensive medical, dental, and vision coverage&nbsp;</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:left;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">401(k) retirement plan&nbsp;</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:left;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Flexible vacation and time-off policy&nbsp;</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:left;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Collaborative, fast-paced, and inclusive work environment&nbsp;</span></li><li style=\"font-size:12pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;text-align:left;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Opportunity to work on&nbsp;cutting-edge&nbsp;technologies with a highly cross-functional team&nbsp;</span></li></ul>",
      "company": "<meta><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><b><strong style=\"font-size:18pt;white-space:pre-wrap;\">About Lyte</strong></b></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:12pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Lyte builds&nbsp;perception&nbsp;systems for Physical AI&nbsp;operating&nbsp;in complex environments. The company combines custom silicon, integrated sensors, and software into a unified platform for robotics, mobility, and next-generation automation. Lyte is headquartered in Sunnyvale, California, with a global presence. For more information, visit </span><a href=\"http://www.lyte.ai\" target=\"_blank\" class=\"css-173makr-linkStyle\" style=\"color:rgb(30,74,169);cursor:pointer;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">www.lyte.ai</span></a></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:12pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><br></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:12pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;text-align:center;\"><b><strong style=\"font-size:13pt;white-space:pre-wrap;\">If&nbsp;you’re&nbsp;excited about building impactful technology in a dynamic, hands-on environment,&nbsp;we’d&nbsp;love to hear from you!</strong></b></p>"
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    "applicationConfirmationTemplate": "69597919867bd28fa68e9bf6",
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  },
  "detail_meta": {
    "url": "https://ats.rippling.com/api/v2/board/lyte/jobs/29ad1382-434b-489f-a0a1-29ea9e92ae35",
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}
Get this page with API

Rendered from the bluedoor Job Postings API. Reproduce it:

GET https://api.bluedoor.sh/job-postings/v1/jobs/6040ca67d7a99ee3da13d13c05f77ffd5e8c0a7b?include=descriptionJSON
GET https://api.bluedoor.sh/job-postings/v1/orgs/3c5bf59d-998c-4877-a152-62bdeba1ec4aJSON
GET https://api.bluedoor.sh/job-postings/v1/sources/f4afde55-a55c-4387-8736-a15d6734cb06JSON
GET https://api.bluedoor.sh/job-postings/v1/jobs/6040ca67d7a99ee3da13d13c05f77ffd5e8c0a7b/eventsJSON