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NPU Architect

Semron · Dresden, DE (primary site) · Active · Personio

Job facts

FieldValue
CompanySemron
TitleNPU Architect
Normalized title-
Department / teamChip Design
LocationDresden, DE, United States
Work model-
Employment typeFull Time
Salary-
Statusactive
ATS providerPersonio
Posted / first seen2025-10-14 / 2026-05-30
Changed / last seen2026-05-30 / 2026-06-06

Related slices

PageWhat it containsOpen
Company jobsActive postings from Semron.Open
Company breakdownsRole, location, ATS, and work model facets for this company.Open
ATS provider jobsActive postings observed through Personio.Open
Provider filtered searchThe same provider as a filtered job collection.Open
City jobsActive postings in Dresden.Open
Department jobsActive postings in Chip Design.Open
Lifecycle eventsOpen, update, close, and reopen events for this posting.Open
Original postingCanonical source or apply URL captured from the ATS.Open

Linked records

CompanySemron
Source61abef5e-84a2-4f60-bcf4-a6a1bcf5067b
ATS providerPersonio

Description

About the Role In this role you'll be responsible to design the next iteration of SEMRON's 3D in-memory compute chip. You will collaborate with a team of hardware, compiler and ML engineers to optimise all aspects of executing ML workloads based on our capacitive analog in-memory matrix-vector multiplication units. What you will do: Design and specify the structure and internal organisation of core architecture modules, aligned with workload requirements and software deployment processes. Partner with the software team to evaluate module performance and efficiency for key workloads, uncover performance constraints, and inform architectural choices. Monitor emerging trends and research in AI workloads, hardware architectures, and applications to guide the evolution of next-generation architectures. What you should bring in: BS/MS/PhD in EE, CS, or a related field Understanding in computer architecture, digital design, and micro-architecture concepts Familiarity with AI/ML algorithms, frameworks, and workloads Programming experience in C/C++ and Python Helpful but not required: Hands-On Experience with ML Hardware Exploration Frameworks like Timeloop, ZigZag, etc. Hands-On Experience with HDLs such as Verilog or System Verilog

Full job record

Job ID5e074683a418e8d7aed829d9cbed895e1583e8ff
Org ID7e9eecd8-ff97-4f83-942a-78c8c866a2d7
Source ID61abef5e-84a2-4f60-bcf4-a6a1bcf5067b
Board ID61abef5e-84a2-4f60-bcf4-a6a1bcf5067b
Providerpersonio
Provider Job Key2385356
TitleNPU Architect
Normalized Title
Statusactive
Activeyes
Location TextDresden, DE (primary site)
DepartmentChip Design
Team
Employment Typefull_time
Workplace Type
Remote Policy
CountryUnited States
RegionDE
CityDresden
Salary Raw
Salary Min
Salary Max
Salary Currency
Salary Period
Source URLhttps://semron.jobs.personio.de/job/2385356?language=en
Apply URLhttps://semron.jobs.personio.de/job/2385356?language=en
First Seen At2026-05-30 05:50:36Z
Last Seen At2026-06-06 07:50:23Z
Last Checked At2026-06-06 07:50:23Z
Last Changed At2026-05-30 05:50:36Z
Inactive At
Source Posted At2025-10-14 13:49:51Z
Source Updated At
Raw Payload Uris3://job-postings-prod-raw-590183727216/raw/provider=personio/board=semron.de/date=2026-06-06/2026-06-06T07-50-22-903Z-ad3463ea873af339a56a00ff3514e5c4cf777237e1cfbc9b012744786f17b539.json
Event Fields
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  "active_status": "active"
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Parsed Structured
{
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  "location": {
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    "city": "Dresden",
    "region": "DE",
    "country": "United States",
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  },
  "remote_policy": null,
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  "workplace_type": null,
  "salary_currency": null
}
Extensions
{}
Native Structured
{
  "id": "2385356",
  "name": "NPU Architect",
  "office": "Dresden, DE (primary site)",
  "keywords": [],
  "schedule": "full-time",
  "createdAt": "2025-10-14T13:49:51+00:00",
  "seniority": "experienced",
  "department": "Chip Design",
  "occupation": "electrical_and_electronics_engineering",
  "subcompany": null,
  "employmentType": "permanent",
  "jobDescriptions": [
    {
      "name": "About the Role",
      "value": "In this role you'll be responsible to design the next iteration of SEMRON's 3D in-memory compute chip. You will collaborate with a team of hardware, compiler and ML engineers to optimise all aspects of executing ML workloads based on our capacitive analog in-memory matrix-vector multiplication units."
    },
    {
      "name": "What you will do:",
      "value": "<ul><li>Design and specify the structure and internal organisation of core architecture modules, aligned with workload requirements and software deployment processes.</li><li>Partner with the software team to evaluate module performance and efficiency for key workloads, uncover performance constraints, and inform architectural choices.</li><li>Monitor emerging trends and research in AI workloads, hardware architectures, and applications to guide the evolution of next-generation architectures.</li></ul>"
    },
    {
      "name": "What you should bring in:",
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    },
    {
      "name": "Helpful but not required:",
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    }
  ],
  "occupationCategory": "engineering",
  "recruitingCategory": null
}
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