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High-Speed Package Design Engineer
Fa Evmr Saasfaprod1 Fa Ocs Oraclecloud Com CX 1 · United States; 600 Mountain Ave - Bldg 02, Murray Hill, New Jersey, US · On Site · Active · Oracle Recruiting Cloud / Fusion HCM
Job facts
| Field | Value |
|---|---|
| Company | Fa Evmr Saasfaprod1 Fa Ocs Oraclecloud Com CX 1 |
| Title | High-Speed Package Design Engineer |
| Normalized title | - |
| Department / team | Pure Research |
| Location | United States |
| Work model | On Site |
| Employment type | Full Time |
| Salary | - |
| Status | active |
| ATS provider | Oracle Recruiting Cloud / Fusion HCM |
| Posted / first seen | 2026-04-09 / 2026-05-31 |
| Changed / last seen | 2026-06-18 / 2026-06-20 |
Related slices
| Page | What it contains | Open |
|---|---|---|
| Company jobs | Active postings from Fa Evmr Saasfaprod1 Fa Ocs Oraclecloud Com CX 1. | Open |
| Company breakdowns | Role, location, ATS, and work model facets for this company. | Open |
| ATS provider jobs | Active postings observed through Oracle Recruiting Cloud / Fusion HCM. | Open |
| Provider filtered search | The same provider as a filtered job collection. | Open |
| Department jobs | Active postings in Pure Research. | Open |
| Work model jobs | Active On Site postings. | Open |
| Lifecycle events | Open, update, close, and reopen events for this posting. | Open |
| Original posting | Canonical source or apply URL captured from the ATS. | Open |
Linked records
| Company | Fa Evmr Saasfaprod1 Fa Ocs Oraclecloud Com CX 1 |
| Source | dbfc4c22-73ba-4fc5-9705-234e3e914c7c |
| ATS provider | Oracle Recruiting Cloud / Fusion HCM |
Description
Description
Nokia Bell Labs is seeking a High-Speed Package Design Engineer to drive the design, simulation, and validation of advanced IC packages for high-performance RF, photonics, and mixed-signal systems.
This role focuses on end-to-end package design ownership, including architecture definition, SI/PI analysis, electromagnetic modeling, and measurement correlation, while working closely with silicon, PCB, and system integration teams. The successful candidate will also contribute to package design enablement through ADKs and reusable libraries, in close collaboration with leading EDA vendors. Package and system design leadership is the primary emphasis of this role.
This position is suitable for senior-level engineers who are comfortable taking ownership of complex package designs while influencing broader design flows and infrastructure.
Responsibilities
Lead the design and development of high-speed IC packages, including SiP, FC-BGA, and advanced heterogeneous integration solutions Define package architectures, stack-ups, routing strategies, and interconnect to meet SI/PI and RF requirements Perform 3D EM simulation and SI/PI analysis of package transitions, passive components, and die-to-package interfaces Co-optimize die, package, and PCB designs in collaboration with silicon, board, and system integration teams Correlate simulation results with laboratory measurements (e.g., VNA, TDR/TDT, high-speed oscilloscope) Contribute to the definition and evolution of package ADKs, reusable libraries, technology files, and verification flows, working in partnership with EDA vendors Provide technical input and design validation for vendor-supported automation and enablement efforts Support continuous improvement of package design methodologies and best practices across projects
Qualifications
Required Qualifications
MS or PhD in Electrical Engineering, Applied Physics, or equivalent relevant industry experience 5+ years of hands-on experience in IC package design for high-speed, RF, or mixed-signal applications Strong fundamentals in electromagnetics, signal integrity, and power integrity Experience with 3D EM and package design tools (e.g., HFSS, CST, ADS, Allegro X APD, Xpedition, or equivalent) Ability to work independently and collaboratively in a cross-functional, research-driven environment
Preferred Qualifications
Experience with advanced packaging technologies (chiplets, 2.5D/3D integration, interposers) Familiarity with ADKs, PDKs, or design enablement concepts, including collaboration with EDA vendors Working knowledge of Python and/or Tcl for design automation, simulation support, or data analysis PCB design and technology (e.g., Altium or equivalent)
Full job record
| Job ID | 5ccce9a5fa87d280c34f6d4a21477635f7198e0c |
| Org ID | 0229f528-a584-4e4f-9943-249cfaac294e |
| Source ID | dbfc4c22-73ba-4fc5-9705-234e3e914c7c |
| Board ID | dbfc4c22-73ba-4fc5-9705-234e3e914c7c |
| Provider | oracle_hcm |
| Provider Job Key | 34144 |
| Title | High-Speed Package Design Engineer |
| Normalized Title | — |
| Status | active |
| Active | yes |
| Location Text | United States; 600 Mountain Ave - Bldg 02, Murray Hill, New Jersey, US |
| Department | Pure Research |
| Team | — |
| Employment Type | full_time |
| Workplace Type | on_site |
| Remote Policy | — |
| Country | United States |
| Region | — |
| City | — |
| Salary Raw | Description Nokia Bell Labs is seeking a High-Speed Package Design Engineer to drive the design, simulation, and validation of advanced IC packages for high-performance RF, photonics, and mixed-signal systems. This role focuses on end-to-end package design ownership, including architecture definition, SI/PI analysis, electromagnetic modeling, and measurement correlation, while working closely with silicon, PCB, and system integration teams. The successful candidate will also contribute to package design enablement through ADKs and reusable libraries, in close collaboration with leading EDA vendors. Package and system design leadership is the primary emphasis of this role. This position is suitable for senior-level engineers who are comfortable taking ownership of complex package designs while influencing broader design flows and infrastructure. Responsibilities Lead the design and development of high-speed IC packages, including SiP, FC-BGA, and advanced heterogeneous integration solutions Define package architectures, stack-ups, routing strategies, and interconnect to meet SI/PI and RF requirements Perform 3D EM simulation and SI/PI analysis of package transitions, passive components, and die-to-package interfaces Co-optimize die, package, and PCB designs in collaboration with silicon, board, and system integration teams Correlate simulation results with laboratory measurements (e.g., VNA, TDR/TDT, high-speed oscilloscope) Contribute to the definition and evolution of package ADKs, reusable libraries, technology files, and verification flows, working in partnership with EDA vendors Provide technical input and design validation for vendor-supported automation and enablement efforts Support continuous improvement of package design methodologies and best practices across projects Qualifications Required Qualifications MS or PhD in Electrical Engineering, Applied Physics, or equivalent relevant industry experience 5+ years of hands-on experience in IC package design for high-speed, RF, or mixed-signal applications Strong fundamentals in electromagnetics, signal integrity, and power integrity Experience with 3D EM and package design tools (e.g., HFSS, CST, ADS, Allegro X APD, Xpedition, or equivalent) Ability to work independently and collaboratively in a cross-functional, research-driven environment Preferred Qualifications Experience with advanced packaging technologies (chiplets, 2.5D/3D integration, interposers) Familiarity with ADKs, PDKs, or design enablement concepts, including collaboration with EDA vendors Working knowledge of Python and/or Tcl for design automation, simulation support, or data analysis PCB design and technology (e.g., Altium or equivalent) |
| Salary Min | — |
| Salary Max | — |
| Salary Currency | — |
| Salary Period | — |
| Source URL | https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/34144 |
| Apply URL | https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/34144 |
| First Seen At | 2026-05-31 18:14:26Z |
| Last Seen At | 2026-06-20 12:43:54Z |
| Last Checked At | 2026-06-20 12:43:54Z |
| Last Changed At | 2026-06-18 11:40:18Z |
| Inactive At | — |
| Source Posted At | 2026-04-09 14:55:15Z |
| Source Updated At | — |
| Raw Payload Uri | s3://job-postings-prod-raw-590183727216/raw/provider=oracle_hcm/board=fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com|CX_1/date=2026-06-20/2026-06-20T12-42-48-078Z-f94b2f8ba8bd1de34082c5b357c79feaf4a6251695e8e887aa3ac82d7e6d8ff4.json |
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