Analog Design Engineer, EU/UK/CH.

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    "description": "<p><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">At<span> </span><span style=\"font-weight: bold\">Kandou</span>, we are redefining the economics of AI infrastructure. Our mission is to<span> </span><span style=\"font-weight: bold\">democratise AI by significantly reducing the Total Cost of Ownership (TCO)<span> </span></span>of hardware systems — a critical barrier to scalable adoption.</span><br></p>\n<p><br><br></p>\n<p><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Our proprietary <span style=\"font-weight: bold\">MIMO-over-copper technology<span> </span></span>powers a<span> </span><span style=\"font-weight: bold\">high-performance, chiplet-based AI memory fabric<span> </span></span>that is both<span> </span><span style=\"font-weight: bold\">scalable and energy-efficient</span>. Unlike traditional interconnects, our solution<span> </span><span style=\"font-weight: bold\">reduces power consumption significantly<span> </span></span>while preserving<span> </span><span style=\"font-weight: bold\">high bandwidth and ultra-low latency<span> </span></span>— unlocking unprecedented efficiency for AI training and inference at scale.</span><br></p>\n<p><br><br></p>\n<p><span style=\"font-family: Inter, sans-serif; font-size: 12pt\">Kandou’s architecture is not just an incremental improvement — it’s a <span style=\"font-weight: bold\">foundational shift<span> </span></span>in how AI hardware is built for the future.</span></p>\n<p><br></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif\">Job title: <span style=\"font-weight: bold\">Analog Design Engineer</span></span></p>\n<p>Location: <span style=\"font-family: arial, helvetica, sans-serif\">EU/CH/UK</span></p>\n<p><br></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-weight: bold\">Key Responsibilities</span></p>\n<ul>\n<li><span style=\"font-family: arial, helvetica, sans-serif\">Position in design, modeling, and verification of custom analog designs for high-speed Serdes transceivers in advanced technology nodes</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif\">Design and verification of analog circuits, following prescribed design and documentation flows, to meet architecture specifications</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif\">If necessary, support and interact with customers on requirements, design specifications, performance results and product delivery</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif\">Support analog IP and chip level integration</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif\">Collaborate with architects, technical leads, analog and digital design, layout, integration, verification, silicon validation and quality teams as needed</span></li>\n</ul>\n<p><br></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-weight: bold\">Competencies </span></p>\n<ul>\n<li><span style=\"font-family: arial, helvetica, sans-serif\">Skilled in the design of high speed analog serdes circuits including DFT, DFM and ESD protection, with a deep knowledge of transistor and wireline communications fundamentals</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif\">Understanding of layout approaches and design techniques used for high-speed and high precision circuits</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif\">Advanced user of EDA tools for design and verification of analog circuits, preferably using the Cadence Virtuoso environment, including their use for simulation, parasitic extraction, electromagnetic modelling, EM/IR and reliability analysis as well as LVS and DRC</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif\">Self-motivated, a strong sense of ownership and responsibility with good verbal and written communication skills and a team player</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif\">Ability to manage and complete designs to schedule using defined design process flows as well as reporting design status  to internal management team</span></li>\n</ul>\n<p><br></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-weight: bold\"> Requirements</span></p>\n<ul>\n<li><span style=\"font-family: arial, helvetica, sans-serif\">The candidate should have a Master's or Ph.D. degree in Electronics or other relevant fields</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif\">Minimum 5 years of experience in analog design and layout of key circuits in multi-gigabit serial data-link transceivers or RF multi tone communications such as equalizers, clock generators, clock and data recovery circuits, TISAR ADC’s, serialisers and output drivers etc.</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif\">Expertise in design and layout of high-speed circuits such as oscillators, phase-locked loops, delay-locked loops, and other fundamental building blocks like biasing, amplifiers, buffers, regulators, filters, ADC,  DAC etc.</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif\">Experience with modern semiconductor process technologies, preferably in finFet technology nodes</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif\">Experience using Ocean, MDL or equivalent to automate analog design verification is highly desirable</span></li>\n</ul>\n<p><span style=\"font-family: arial, helvetica, sans-serif\"><br></span></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif\"><span>If this is the role you have been looking for and want to be part of a growing company with an exciting future, we would really love to hear from you. Together We Kandou It!</span></span></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif\"><br></span></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif\"><span><span style=\"color: rgb(34, 34, 34); font-family: Arial, sans-serif\">Visit us at </span><a href=\"https://www.kandou.ai/\" target=\"_blank\" rel=\"noopener noreferrer\">www.kandou.ai</a><span style=\"color: rgb(34, 34, 34); font-family: Arial, sans-serif\"> and </span><a href=\"https://www.linkedin.com/company/kandou-ai/posts?lipi=urn%3Ali%3Apage%3Acompanies_company_index%3Bd9883c75-e180-4084-9488-1a503e730cfe\" target=\"_blank\" rel=\"noopener noreferrer\">https://www.linkedin.com/company/kandou-ai/</a></span></span></p>",
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