Senior Electrical Engineer (FPGA / High-Speed / Mixed-Signal)

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    "heading": "Senior Electrical Engineer (FPGA / High-Speed / Mixed-Signal)",
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    "description_html": "<br>Key Responsibilities<br>1. FPGA-Based System Architecture<br>•<br>Define FPGA-centric system architectures for high-throughput data processing platforms<br>•<br>Partition functionality across FPGA, ADC/DAC, and host interfaces<br>•<br>Collaborate with FPGA/FW teams on interface definition, timing, and performance<br>2. High-Speed Digital & SerDes Design<br>•<br>Design and integrate high-speed interfaces including:<br>o<br>DDR4/DDR memory subsystems<br>o<br>PCIe Gen3/Gen4 interfaces<br>o<br>QSFP (10G/25G/40G/100G) links<br>o<br>10G+ SerDes channels<br>•<br>Define routing constraints, stack-up, and impedance control<br>•<br>Ensure signal integrity, timing closure, and link stability<br>Public<br>3. Mixed-Signal & Analog Front-End Design<br>•<br>Design and integrate:<br>o<br>High-speed ADC/DAC signal chains<br>o<br>Data Converter Architectures (DCA)<br>o<br>Precision analog front-end (AFE) circuits<br>•<br>Develop circuits using low-noise OpAmps, filters, and gain stages<br>•<br>Optimize performance metrics such as SNR, ENOB, bandwidth, and jitter sensitivity<br>4. Power System Design<br>•<br>Design multi-rail DC/DC power systems for FPGA and high-speed circuits<br>•<br>Manage power sequencing, noise, ripple, and efficiency<br>•<br>Ensure power integrity for sensitive ADC and high-speed SerDes subsystems<br>5. Hardware Design & PCB Implementation<br>•<br>Own schematic design and hardware architecture (Xpedition preferred)<br>•<br>Guide PCB layout for high-layer-count, high-speed boards<br>•<br>Lead design reviews focusing on SI/PI/EMI risks<br>•<br>Ensure manufacturability (DFM) and testability (DFT)<br>6. System Bring-up & Debug<br>•<br>Lead board bring-up and system integration:<br>o<br>DDR training<br>o<br>PCIe and SerDes link-up<br>o<br>ADC performance validation<br>•<br>Debug issues related to:<br>o<br>Signal integrity<br>Public<br>o<br>Jitter and noise<br>o<br>Power coupling and system interaction<br>•<br>Use lab tools such as oscilloscopes, TDR/VNA, and protocol analyzers<br>7. Cross-Functional Collaboration<br>•<br>Work closely with FPGA, firmware, software, mechanical, and system engineering teams<br>•<br>Align electrical design with system-level performance requirements<br>•<br>Drive cross-domain trade-offs<br>8. Technical Leadership<br>•<br>Lead architectural decisions and technical reviews<br>•<br>Mentor junior engineers in high-speed and mixed-signal design<br>•<br>Drive structured problem-solving across complex systems<br>Required Qualifications<br>•<br>Bachelor’s or Master’s degree in Electrical Engineering or related field<br>•<br>8–12+ years of experience in high-speed, FPGA, or mixed-signal systems<br>Core Technical Requirements<br>•<br>FPGA-based system design experience<br>•<br>DDR4 memory subsystem design experience<br>•<br>PCIe / SerDes / high-speed link experience<br>•<br>ADC and analog front-end design experience<br>•<br>DC/DC power system design experience<br>Fundamentals<br>•<br>Strong understanding of:<br>Public<br>o<br>Signal Integrity (SI)<br>o<br>Power Integrity (PI)<br>o<br>High-speed timing and jitter analysis<br>Preferred Qualifications<br>•<br>Hands-on experience with FPGA platforms (Intel / Xilinx)<br>•<br>Experience with:<br>o<br>High-speed data converters<br>o<br>Optical interfaces / QSFP modules<br>o<br>JESD204 or similar high-speed data links<br>•<br>Strong PCB design experience with high-speed constraints<br>•<br>Experience with tools such as:<br>o<br>Xpedition (Mentor / Siemens)<br>o<br>SI/PI analysis tools<br>Strong Plus<br>•<br>Experience in semiconductor equipment, imaging, or instrumentation systems<br>•<br>Experience with multi-board or modular systems<br>•<br>Understanding of signal-power-thermal coupling effects<br>•<br>Full product lifecycle experience (R&D → NPI → production)<br>Soft Skills<br>•<br>Strong ownership mindset and accountability<br>•<br>Ability to solve complex multi-domain engineering problems<br>•<br>Excellent communication and cross-functional collaboration skills",
    "description_text": "Key Responsibilities\n1. FPGA-Based System Architecture\n•\nDefine FPGA-centric system architectures for high-throughput data processing platforms\n•\nPartition functionality across FPGA, ADC/DAC, and host interfaces\n•\nCollaborate with FPGA/FW teams on interface definition, timing, and performance\n2. High-Speed Digital & SerDes Design\n•\nDesign and integrate high-speed interfaces including:\no\nDDR4/DDR memory subsystems\no\nPCIe Gen3/Gen4 interfaces\no\nQSFP (10G/25G/40G/100G) links\no\n10G+ SerDes channels\n•\nDefine routing constraints, stack-up, and impedance control\n•\nEnsure signal integrity, timing closure, and link stability\nPublic\n3. Mixed-Signal & Analog Front-End Design\n•\nDesign and integrate:\no\nHigh-speed ADC/DAC signal chains\no\nData Converter Architectures (DCA)\no\nPrecision analog front-end (AFE) circuits\n•\nDevelop circuits using low-noise OpAmps, filters, and gain stages\n•\nOptimize performance metrics such as SNR, ENOB, bandwidth, and jitter sensitivity\n4. Power System Design\n•\nDesign multi-rail DC/DC power systems for FPGA and high-speed circuits\n•\nManage power sequencing, noise, ripple, and efficiency\n•\nEnsure power integrity for sensitive ADC and high-speed SerDes subsystems\n5. Hardware Design & PCB Implementation\n•\nOwn schematic design and hardware architecture (Xpedition preferred)\n•\nGuide PCB layout for high-layer-count, high-speed boards\n•\nLead design reviews focusing on SI/PI/EMI risks\n•\nEnsure manufacturability (DFM) and testability (DFT)\n6. System Bring-up & Debug\n•\nLead board bring-up and system integration:\no\nDDR training\no\nPCIe and SerDes link-up\no\nADC performance validation\n•\nDebug issues related to:\no\nSignal integrity\nPublic\no\nJitter and noise\no\nPower coupling and system interaction\n•\nUse lab tools such as oscilloscopes, TDR/VNA, and protocol analyzers\n7. Cross-Functional Collaboration\n•\nWork closely with FPGA, firmware, software, mechanical, and system engineering teams\n•\nAlign electrical design with system-level performance requirements\n•\nDrive cross-domain trade-offs\n8. Technical Leadership\n•\nLead architectural decisions and technical reviews\n•\nMentor junior engineers in high-speed and mixed-signal design\n•\nDrive structured problem-solving across complex systems\nRequired Qualifications\n•\nBachelor’s or Master’s degree in Electrical Engineering or related field\n•\n8–12+ years of experience in high-speed, FPGA, or mixed-signal systems\nCore Technical Requirements\n•\nFPGA-based system design experience\n•\nDDR4 memory subsystem design experience\n•\nPCIe / SerDes / high-speed link experience\n•\nADC and analog front-end design experience\n•\nDC/DC power system design experience\nFundamentals\n•\nStrong understanding of:\nPublic\no\nSignal Integrity (SI)\no\nPower Integrity (PI)\no\nHigh-speed timing and jitter analysis\nPreferred Qualifications\n•\nHands-on experience with FPGA platforms (Intel / Xilinx)\n•\nExperience with:\no\nHigh-speed data converters\no\nOptical interfaces / QSFP modules\no\nJESD204 or similar high-speed data links\n•\nStrong PCB design experience with high-speed constraints\n•\nExperience with tools such as:\no\nXpedition (Mentor / Siemens)\no\nSI/PI analysis tools\nStrong Plus\n•\nExperience in semiconductor equipment, imaging, or instrumentation systems\n•\nExperience with multi-board or modular systems\n•\nUnderstanding of signal-power-thermal coupling effects\n•\nFull product lifecycle experience (R&D → NPI → production)\nSoft Skills\n•\nStrong ownership mindset and accountability\n•\nAbility to solve complex multi-domain engineering problems\n•\nExcellent communication and cross-functional collaboration skills",
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      "description": "<br>Key Responsibilities<br>1. FPGA-Based System Architecture<br>•<br>Define FPGA-centric system architectures for high-throughput data processing platforms<br>•<br>Partition functionality across FPGA, ADC/DAC, and host interfaces<br>•<br>Collaborate with FPGA/FW teams on interface definition, timing, and performance<br>2. High-Speed Digital & SerDes Design<br>•<br>Design and integrate high-speed interfaces including:<br>o<br>DDR4/DDR memory subsystems<br>o<br>PCIe Gen3/Gen4 interfaces<br>o<br>QSFP (10G/25G/40G/100G) links<br>o<br>10G+ SerDes channels<br>•<br>Define routing constraints, stack-up, and impedance control<br>•<br>Ensure signal integrity, timing closure, and link stability<br>Public<br>3. Mixed-Signal & Analog Front-End Design<br>•<br>Design and integrate:<br>o<br>High-speed ADC/DAC signal chains<br>o<br>Data Converter Architectures (DCA)<br>o<br>Precision analog front-end (AFE) circuits<br>•<br>Develop circuits using low-noise OpAmps, filters, and gain stages<br>•<br>Optimize performance metrics such as SNR, ENOB, bandwidth, and jitter sensitivity<br>4. Power System Design<br>•<br>Design multi-rail DC/DC power systems for FPGA and high-speed circuits<br>•<br>Manage power sequencing, noise, ripple, and efficiency<br>•<br>Ensure power integrity for sensitive ADC and high-speed SerDes subsystems<br>5. Hardware Design & PCB Implementation<br>•<br>Own schematic design and hardware architecture (Xpedition preferred)<br>•<br>Guide PCB layout for high-layer-count, high-speed boards<br>•<br>Lead design reviews focusing on SI/PI/EMI risks<br>•<br>Ensure manufacturability (DFM) and testability (DFT)<br>6. System Bring-up & Debug<br>•<br>Lead board bring-up and system integration:<br>o<br>DDR training<br>o<br>PCIe and SerDes link-up<br>o<br>ADC performance validation<br>•<br>Debug issues related to:<br>o<br>Signal integrity<br>Public<br>o<br>Jitter and noise<br>o<br>Power coupling and system interaction<br>•<br>Use lab tools such as oscilloscopes, TDR/VNA, and protocol analyzers<br>7. Cross-Functional Collaboration<br>•<br>Work closely with FPGA, firmware, software, mechanical, and system engineering teams<br>•<br>Align electrical design with system-level performance requirements<br>•<br>Drive cross-domain trade-offs<br>8. Technical Leadership<br>•<br>Lead architectural decisions and technical reviews<br>•<br>Mentor junior engineers in high-speed and mixed-signal design<br>•<br>Drive structured problem-solving across complex systems<br>Required Qualifications<br>•<br>Bachelor’s or Master’s degree in Electrical Engineering or related field<br>•<br>8–12+ years of experience in high-speed, FPGA, or mixed-signal systems<br>Core Technical Requirements<br>•<br>FPGA-based system design experience<br>•<br>DDR4 memory subsystem design experience<br>•<br>PCIe / SerDes / high-speed link experience<br>•<br>ADC and analog front-end design experience<br>•<br>DC/DC power system design experience<br>Fundamentals<br>•<br>Strong understanding of:<br>Public<br>o<br>Signal Integrity (SI)<br>o<br>Power Integrity (PI)<br>o<br>High-speed timing and jitter analysis<br>Preferred Qualifications<br>•<br>Hands-on experience with FPGA platforms (Intel / Xilinx)<br>•<br>Experience with:<br>o<br>High-speed data converters<br>o<br>Optical interfaces / QSFP modules<br>o<br>JESD204 or similar high-speed data links<br>•<br>Strong PCB design experience with high-speed constraints<br>•<br>Experience with tools such as:<br>o<br>Xpedition (Mentor / Siemens)<br>o<br>SI/PI analysis tools<br>Strong Plus<br>•<br>Experience in semiconductor equipment, imaging, or instrumentation systems<br>•<br>Experience with multi-board or modular systems<br>•<br>Understanding of signal-power-thermal coupling effects<br>•<br>Full product lifecycle experience (R&D → NPI → production)<br>Soft Skills<br>•<br>Strong ownership mindset and accountability<br>•<br>Ability to solve complex multi-domain engineering problems<br>•<br>Excellent communication and cross-functional collaboration skills",
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