Principal Firmware Engineer, AI Platform

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    "ExternalDescriptionStr": "<p>We are looking for a <strong>Principal Firmware Engineer </strong>to lead the integration and control of our next-generation AI accelerators. As our products evolve to include dedicated neural network hardware, the challenge shifts from pure algorithm implementation to complex hardware orchestration.</p>\n<p>This role is about more than just writing kernels; it’s about defining the firmware layer that sits between high-level AI frameworks and our custom silicon. You will be responsible for how our DSPs manage, schedule, and feed data to these accelerators. We need a veteran who can look at a PyTorch model and determine the best way to tile memory, manage DMA transfers, and synchronize processing to ensure we hit our ultra-low-power targets while maximizing throughput. You will also be the primary technical voice influencing our future hardware specs to ensure our accelerators are actually \"firmware-friendly.\"</p>",
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    "CorporateDescriptionStr": "<div>\n <b>onsemi&nbsp;</b><span class=\"ui-provider\">(Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.<br></span>\n</div>\n<div>\n <span class=\"ui-provider\"><br></span>\n</div>\n<div>\n <p style=\"margin: 0in\"><b><span style=\"font-weight: normal\">More details about our company benefits can be found here:</span></b></p>\n <p style=\"margin: 0in\"><a href=\"https://www.onsemi.com/careers/career-benefits\" target=\"_blank\" rel=\"nofollow\">https://www.onsemi.com/careers/career-benefits</a></p>\n</div>",
    "ExternalPostedStartDate": "2026-05-21T14:14:23+00:00",
    "ExternalQualificationsStr": "<p><strong>Must-Haves:</strong></p>\n<ul>\n <li><strong>15+ years of firmware development experience</strong>, with a heavy focus on hardware/software co-design and controlling custom accelerators or NPUs.</li>\n <li><strong>Deep Hardware Interfacing Knowledge:</strong> Expert-level understanding of DMA, memory-mapped I/O, interrupts, and synchronization between CPU/DSP and specialized hardware blocks.</li>\n <li><strong>AI Framework Literacy:</strong> Strong grasp of the PyTorch/TensorFlow ecosystem and how high-level graphs are lowered and quantized for embedded deployment.</li>\n <li><strong>Bare-Metal Mastery:</strong> Expert-level C and a \"thinking in hardware\" mindset; you should be comfortable reading a hardware spec and identifying the firmware bottlenecks before the silicon is even made.</li>\n <li><strong>Resource-Constrained Optimization:</strong> Proven experience squeezing performance out of systems with very limited memory (KB) and strict power budgets.</li>\n <li><strong>Communication:</strong> Ability to explain complex hardware-to-firmware trade-offs to senior leadership and provide technical leadership across cross-functional teams.</li>\n</ul>\n<p><strong>Nice-to-Haves:</strong></p>\n<ul>\n <li>Experience building or using <strong>AI compilers or toolchains</strong> (e.g., TVM, MLIR, or custom IRs).</li>\n <li>Background in <strong>ultra-low-power DSPs</strong> (audiology, wearables, or medical devices).</li>\n <li>Experience with ARM Cortex-M or proprietary DSP architectures and their specific bus protocols.</li>\n <li>Knowledge of fixed-point arithmetic and its impact on neural network performance and power.</li>\n</ul>",
    "InternalQualificationsStr": "<p><strong>Must-Haves:</strong></p>\n<ul>\n <li><strong>15+ years of firmware development experience</strong>, with a heavy focus on hardware/software co-design and controlling custom accelerators or NPUs.</li>\n <li><strong>Deep Hardware Interfacing Knowledge:</strong> Expert-level understanding of DMA, memory-mapped I/O, interrupts, and synchronization between CPU/DSP and specialized hardware blocks.</li>\n <li><strong>AI Framework Literacy:</strong> Strong grasp of the PyTorch/TensorFlow ecosystem and how high-level graphs are lowered and quantized for embedded deployment.</li>\n <li><strong>Bare-Metal Mastery:</strong> Expert-level C and a \"thinking in hardware\" mindset; you should be comfortable reading a hardware spec and identifying the firmware bottlenecks before the silicon is even made.</li>\n <li><strong>Resource-Constrained Optimization:</strong> Proven experience squeezing performance out of systems with very limited memory (KB) and strict power budgets.</li>\n <li><strong>Communication:</strong> Ability to explain complex hardware-to-firmware trade-offs to senior leadership and provide technical leadership across cross-functional teams.</li>\n</ul>\n<p><strong>Nice-to-Haves:</strong></p>\n<ul>\n <li>Experience building or using <strong>AI compilers or toolchains</strong> (e.g., TVM, MLIR, or custom IRs).</li>\n <li>Background in <strong>ultra-low-power DSPs</strong> (audiology, wearables, or medical devices).</li>\n <li>Experience with ARM Cortex-M or proprietary DSP architectures and their specific bus protocols.</li>\n <li>Knowledge of fixed-point arithmetic and its impact on neural network performance and power.</li>\n</ul>",
    "OrganizationDescriptionStr": "<span>We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.</span><span></span>\n<div>\n <br/>\n</div>\n<div>\n <br/>\n</div>\n<div>\n <b>onsemi</b>&nbsp;is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, ethnicity, color, religion, ancestry, national origin, age, marital status, pregnancy, sex, sexual orientation, physical or mental disability, medical condition, genetic information, military or veteran status, gender identity, gender expression, or any other protected category under applicable federal, state, or local laws.\n</div>\n<div>\n <br/>\n</div>\n<div>\n If you are an individual with a disability and require a reasonable accommodation to complete any part of the application process, or are limited in the ability or unable to access or use this online application process and need an alternative method for applying, you may contact&nbsp;<span><a href=\"mailto:[email protected]\" target=\"_blank\">[email protected]</a></span> for assistance.\n</div>",
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    "ExternalResponsibilitiesStr": "<ul>\n <li><strong>Architect Accelerator Orchestration:</strong> Define and implement the firmware control logic, drivers, and scheduling required to manage dedicated neural network accelerators from the DSP/MCU.</li>\n <li><strong>Bridge the AI Flow:</strong> Develop the toolchain strategy that translates PyTorch/TensorFlow models into optimized hardware-specific instructions and memory layouts.</li>\n <li><strong>Optimize Data Movement:</strong> Design efficient DMA and memory tiling strategies to minimize power consumption and latency when moving data between memory and AI hardware blocks.</li>\n <li><strong>Influence Silicon Design:</strong> Serve as the lead firmware stakeholder in hardware/software co-design, ensuring that future hardware accelerators have the right registers, interrupts, and memory interfaces for efficient control.</li>\n <li><strong>Customer Technical Interface:</strong> Act as the \"deep-tech\" lead for customers, providing the architectural guidance they need to deploy sophisticated models on our specific hardware/firmware stack.</li>\n <li><strong>Performance Bottleneck Analysis:</strong> Identify and resolve performance gaps in the interaction between the DSP and the accelerator, moving beyond \"it works\" to \"it's optimal.\"</li>\n <li><strong>Technical Mentorship:</strong> Lead the broader firmware team in modern AI deployment techniques, setting the standard for production-quality, hardware-abstracted code.</li>\n</ul>",
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