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Analog and RF layout engineer W2 Hiring
Pddninc · Sunnyvale, CA, United States · Active · SmartRecruiters
Job facts
| Field | Value |
|---|---|
| Company | Pddninc |
| Title | Analog and RF layout engineer W2 Hiring |
| Normalized title | - |
| Department / team | Information Technology |
| Location | Sunnyvale, CA, United States |
| Work model | - |
| Employment type | Contract |
| Salary | - |
| Status | active |
| ATS provider | SmartRecruiters |
| Posted / first seen | 2026-04-27 / 2026-05-31 |
| Changed / last seen | 2026-05-31 / 2026-06-06 |
Related slices
| Page | What it contains | Open |
|---|---|---|
| Company jobs | Active postings from Pddninc. | Open |
| Company breakdowns | Role, location, ATS, and work model facets for this company. | Open |
| ATS provider jobs | Active postings observed through SmartRecruiters. | Open |
| Provider filtered search | The same provider as a filtered job collection. | Open |
| City jobs | Active postings in Sunnyvale. | Open |
| Department jobs | Active postings in Information Technology. | Open |
| Lifecycle events | Open, update, close, and reopen events for this posting. | Open |
| Original posting | Canonical source or apply URL captured from the ATS. | Open |
Linked records
| Company | Pddninc |
| Source | a1109271-b6c4-489f-a0c4-e61ba8d1af63 |
| ATS provider | SmartRecruiters |
Description
Role: Analog and RF layout engineer
Work location: Sunnyvale, CA
Job Type: Contract
Interview: Phone/Skype
Job Description:
• Minimum 6+ years of experience in Analog and RF layout.
• Experience developing and leading complex layout IC for high-speed applications in advanced CMOS FinFET technologies such as 7nm and below at the block level and chip level.
• Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys.
• Experience with layout of high-performance high-speed analog mixed-signal blocks such Transceivers, CMOS drivers, high-speed Data converters and PLLs.
• Experience with floor planning, block level routing and top-level chip assemble.
• Knowledge of layout techniques such as floor planning, layer generation, thermal aware layout with consideration for electro-migration.
Key Responsibilities:
developing and leading complex layout IC for high-speed applications in advanced CMOS FinFET technologies such as 7nm and below at the block level and chip level
What are the Mandatory skills and skill proficiencies required for this position?
advanced CMOS FinFET technologies such as 7nm and below at the block level and chip level. Experience with floor planning, block level routing and top-level chip assemble. Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys.
What are the Optional skills and skill proficiencies for this position?
Knowledge of layout techniques such as floor planning, layer generation, thermal aware layout with consideration for electro-migration.
All your information will be kept confidential according to EEO guidelines.
Full job record
| Job ID | 4be8de99e0bdec208eb86990d8ee3cc825210e19 |
| Org ID | d6682192-c922-4608-a13c-f57ff59e4585 |
| Source ID | a1109271-b6c4-489f-a0c4-e61ba8d1af63 |
| Board ID | a1109271-b6c4-489f-a0c4-e61ba8d1af63 |
| Provider | smartrecruiters |
| Provider Job Key | 744000123264542 |
| Title | Analog and RF layout engineer W2 Hiring |
| Normalized Title | — |
| Status | active |
| Active | yes |
| Location Text | Sunnyvale, CA, United States |
| Department | Information Technology |
| Team | — |
| Employment Type | contract |
| Workplace Type | — |
| Remote Policy | — |
| Country | United States |
| Region | CA |
| City | Sunnyvale |
| Salary Raw | Role: Analog and RF layout engineer Work location: Sunnyvale, CA Job Type: Contract Interview: Phone/Skype Job Description: • Minimum 6+ years of experience in Analog and RF layout. • Experience developing and leading complex layout IC for high-speed applications in advanced CMOS FinFET technologies such as 7nm and below at the block level and chip level. • Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys. • Experience with layout of high-performance high-speed analog mixed-signal blocks such Transceivers, CMOS drivers, high-speed Data converters and PLLs. • Experience with floor planning, block level routing and top-level chip assemble. • Knowledge of layout techniques such as floor planning, layer generation, thermal aware layout with consideration for electro-migration. Key Responsibilities: developing and leading complex layout IC for high-speed applications in advanced CMOS FinFET technologies such as 7nm and below at the block level and chip level What are the Mandatory skills and skill proficiencies required for this position? advanced CMOS FinFET technologies such as 7nm and below at the block level and chip level. Experience with floor planning, block level routing and top-level chip assemble. Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys. What are the Optional skills and skill proficiencies for this position? Knowledge of layout techniques such as floor planning, layer generation, thermal aware layout with consideration for electro-migration. All your information will be kept confidential according to EEO guidelines. |
| Salary Min | — |
| Salary Max | — |
| Salary Currency | — |
| Salary Period | — |
| Source URL | https://jobs.smartrecruiters.com/PDDNINC/744000123264542-analog-and-rf-layout-engineer-w2-hiring |
| Apply URL | https://jobs.smartrecruiters.com/PDDNINC/744000123264542-analog-and-rf-layout-engineer-w2-hiring?oga=true |
| First Seen At | 2026-05-31 17:42:37Z |
| Last Seen At | 2026-06-06 10:47:48Z |
| Last Checked At | 2026-06-06 10:47:48Z |
| Last Changed At | 2026-05-31 17:42:37Z |
| Inactive At | — |
| Source Posted At | 2026-04-27 17:45:46Z |
| Source Updated At | — |
| Raw Payload Uri | s3://job-postings-prod-raw-590183727216/raw/provider=smartrecruiters/board=pddninc/date=2026-06-06/2026-06-06T10-47-46-670Z-07c085f9b8ffb89a5ecae8f9b295f3f887fc2933687bdf0d170fb28af15473e7.json |
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