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HomeCompaniesPddnincAnalog and RF layout engineer W2 Hiring

Analog and RF layout engineer W2 Hiring

Pddninc · Sunnyvale, CA, United States · Active · SmartRecruiters

Job facts

FieldValue
CompanyPddninc
TitleAnalog and RF layout engineer W2 Hiring
Normalized title-
Department / teamInformation Technology
LocationSunnyvale, CA, United States
Work model-
Employment typeContract
Salary-
Statusactive
ATS providerSmartRecruiters
Posted / first seen2026-04-27 / 2026-05-31
Changed / last seen2026-05-31 / 2026-06-06

Related slices

PageWhat it containsOpen
Company jobsActive postings from Pddninc.Open
Company breakdownsRole, location, ATS, and work model facets for this company.Open
ATS provider jobsActive postings observed through SmartRecruiters.Open
Provider filtered searchThe same provider as a filtered job collection.Open
City jobsActive postings in Sunnyvale.Open
Department jobsActive postings in Information Technology.Open
Lifecycle eventsOpen, update, close, and reopen events for this posting.Open
Original postingCanonical source or apply URL captured from the ATS.Open

Linked records

CompanyPddninc
Sourcea1109271-b6c4-489f-a0c4-e61ba8d1af63
ATS providerSmartRecruiters

Description

Role: Analog and RF layout engineer Work location: Sunnyvale, CA Job Type: Contract Interview: Phone/Skype Job Description: • Minimum 6+ years of experience in Analog and RF layout. • Experience developing and leading complex layout IC for high-speed applications in advanced CMOS FinFET technologies such as 7nm and below at the block level and chip level. • Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys. • Experience with layout of high-performance high-speed analog mixed-signal blocks such Transceivers, CMOS drivers, high-speed Data converters and PLLs. • Experience with floor planning, block level routing and top-level chip assemble. • Knowledge of layout techniques such as floor planning, layer generation, thermal aware layout with consideration for electro-migration. Key Responsibilities: developing and leading complex layout IC for high-speed applications in advanced CMOS FinFET technologies such as 7nm and below at the block level and chip level What are the Mandatory skills and skill proficiencies required for this position? advanced CMOS FinFET technologies such as 7nm and below at the block level and chip level. Experience with floor planning, block level routing and top-level chip assemble. Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys. What are the Optional skills and skill proficiencies for this position? Knowledge of layout techniques such as floor planning, layer generation, thermal aware layout with consideration for electro-migration. All your information will be kept confidential according to EEO guidelines.

Full job record

Job ID4be8de99e0bdec208eb86990d8ee3cc825210e19
Org IDd6682192-c922-4608-a13c-f57ff59e4585
Source IDa1109271-b6c4-489f-a0c4-e61ba8d1af63
Board IDa1109271-b6c4-489f-a0c4-e61ba8d1af63
Providersmartrecruiters
Provider Job Key744000123264542
TitleAnalog and RF layout engineer W2 Hiring
Normalized Title
Statusactive
Activeyes
Location TextSunnyvale, CA, United States
DepartmentInformation Technology
Team
Employment Typecontract
Workplace Type
Remote Policy
CountryUnited States
RegionCA
CitySunnyvale
Salary RawRole: Analog and RF layout engineer Work location: Sunnyvale, CA Job Type: Contract Interview: Phone/Skype Job Description: • Minimum 6+ years of experience in Analog and RF layout. • Experience developing and leading complex layout IC for high-speed applications in advanced CMOS FinFET technologies such as 7nm and below at the block level and chip level. • Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys. • Experience with layout of high-performance high-speed analog mixed-signal blocks such Transceivers, CMOS drivers, high-speed Data converters and PLLs. • Experience with floor planning, block level routing and top-level chip assemble. • Knowledge of layout techniques such as floor planning, layer generation, thermal aware layout with consideration for electro-migration. Key Responsibilities: developing and leading complex layout IC for high-speed applications in advanced CMOS FinFET technologies such as 7nm and below at the block level and chip level What are the Mandatory skills and skill proficiencies required for this position? advanced CMOS FinFET technologies such as 7nm and below at the block level and chip level. Experience with floor planning, block level routing and top-level chip assemble. Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys. What are the Optional skills and skill proficiencies for this position? Knowledge of layout techniques such as floor planning, layer generation, thermal aware layout with consideration for electro-migration. All your information will be kept confidential according to EEO guidelines.
Salary Min
Salary Max
Salary Currency
Salary Period
Source URLhttps://jobs.smartrecruiters.com/PDDNINC/744000123264542-analog-and-rf-layout-engineer-w2-hiring
Apply URLhttps://jobs.smartrecruiters.com/PDDNINC/744000123264542-analog-and-rf-layout-engineer-w2-hiring?oga=true
First Seen At2026-05-31 17:42:37Z
Last Seen At2026-06-06 10:47:48Z
Last Checked At2026-06-06 10:47:48Z
Last Changed At2026-05-31 17:42:37Z
Inactive At
Source Posted At2026-04-27 17:45:46Z
Source Updated At
Raw Payload Uris3://job-postings-prod-raw-590183727216/raw/provider=smartrecruiters/board=pddninc/date=2026-06-06/2026-06-06T10-47-46-670Z-07c085f9b8ffb89a5ecae8f9b295f3f887fc2933687bdf0d170fb28af15473e7.json
Event Fields
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Parsed Structured
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Extensions
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