Senior FPGA Engineer

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    "description": "<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Tangram Flex is seeking a <span style=\"font-weight: bold\">Senior FPGA Engineer</span> with a Software/Firmware Focus will design, develop, and optimize high-performance digital logic circuits. This role bridges the gap between hardware architecture and low-level software. The engineer is responsible for implementing complex digital signal processing (DSP) algorithms, managing high-speed data protocols, and ensuring seamless integration with host software systems.</span></p>\n<p><br></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\"><span style=\"font-weight: bold\">What We Do:</span> Our team and products provide solutions to enable innovators to design, develop, verify, and advance critical systems, while accelerating innovation that advances our nations’ security. By accelerating delivery of critical systems, Tangram is  transforming the way our nation solves complex software challenges.</span></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">  </span></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; font-weight: bold\">JOB RESPONSIBILITIES/</span></p>\n<ul>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Architecture &amp; Design: Translate complex software requirements into optimized Register Transfer Level (RTL) architecture. </span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">IP Development: Design, implement, and test custom intellectual property (IP) blocks using VHDL, Verilog, or SystemVerilog. </span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Hardware-Software Integration: Develop low-level C/C++ drivers, Linux kernel modules, and APIs to connect FPGA logic with embedded microprocessors.</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Verification &amp; Testing: Write comprehensive testbenches (using UVM or SystemVerilog) and utilize hardware-in-the-loop (HIL) testing with oscilloscopes and logic analyzers. </span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Timing Closure: Analyze and optimize logic placement, routing, and clock domains to meet strict hardware timing and power constraints.</span></li>\n</ul>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; font-weight: bold\">DESIRED SKILLS &amp; EXPERIENCE/</span></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; font-style: italic\">Required Skills:</span></p>\n<ul>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering or a related field</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Ability to obtain or possess a current/or recent U.S. Government Security (DoD) Clearance. U.S. citizenship is required to obtain clearance</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Hardware Languages: Proficiency in VHDL, Verilog, or System Verilog.</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Software Languages: Strong programming skills in C, C++, and scripting languages like Python or Tcl for automation.</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">FPGA Toolchains: Mastery of vendor tools such as AMD/Xilinx Vivado, Intel Quartus, or Microchip Libero.</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Methodologies: Experience with High-Level Synthesis (HLS), Digital Signal Processing (DSP), and SoC architectures (e.g., ARM-Cortex embedded in FPGA).</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Protocols: Deep understanding of high-speed interfaces like PCIe, Ethernet (10G/100G), DDR4/DDR5, and AXI streaming.</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Work is based in Dayton, Ohio with periodic days at WPAFB</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Travel required up to 25% for customer support and presentations</span></li>\n</ul>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; font-style: italic\">Desired Skills:</span></p>\n<ul>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Experience: 5+ years of hands-on experience in FPGA design and embedded software development.</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Domain Expertise: Industry-specific experience in areas like RF/SDR, defense, automotive (ADAS), high-frequency trading, or data centers. </span></li>\n</ul>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; font-style: italic\">Physical Requirements: </span></p>\n<ul>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Ability to travel by air, car, or other transportation methods</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Prolonged periods of sitting at a desk and working on a computer (up to 8 hours/day)</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Ability to lift and carry lightweight items (e.g., laptops, demo equipment, marketing materials) up to 25 lbs.</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Frequent use of hands and fingers for typing, using a mouse, writing, and handling equipment.</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Visual acuity to read detailed technical documents, view computer screens, and operate software systems</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Auditory ability to participate in meetings, customer demos, and conference calls, including in potentially noisy environments (e.g., trade shows or military facilities)</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Mobility to move between office spaces, customer sites, conference venues, and manufacturing or lab environments</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Flexibility to adapt to varying work environments (e.g., corporate offices, government buildings, industrial or lab spaces)</span></li>\n</ul>\n<p><br></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">We are committed to staying rooted in our core value of Team First. For that reason, we've designed a highly competitive benefits program and supportive work environment to engage employees and their families.</span></p>\n<ul>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Hybrid work options </span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Flexible Working Hours, 10 paid holidays, and generous Paid Time Off</span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Employer Paid Medical, Dental, Vision and Short and Long Term Disability Insurance </span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Access to group rating plans for Life Insurance </span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Employer contribution to Health Savings Account  </span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Competitive 401K employer match </span></li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">A work environment and culture that fosters transparency, collaboration and well-being </span></li>\n</ul>\n<p><br></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Tangram Flex is an Equal Opportunity Employer, and provides reasonable accommodation for qualified individuals with disabilities and disabled veterans in its application procedures and in accordance with federal law.  All qualified candidates will receive consideration for employment based on business needs, job requirements, and individual qualifications. </span></p>\n<p><br></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">EEO/AA Vet/Disabled Employer/ and E-Verify</span></p>",
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