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Sr. Hardware Design Engineer (Remote)
FortifyIQ · Remote · Remote · Active · Greenhouse
Job facts
| Field | Value |
|---|---|
| Company | FortifyIQ |
| Title | Sr. Hardware Design Engineer (Remote) |
| Normalized title | - |
| Department / team | IT Support |
| Location | United States |
| Work model | Remote / Remote |
| Employment type | - |
| Salary | - |
| Status | active |
| ATS provider | Greenhouse |
| Posted / first seen | 2026-02-12 / 2026-05-29 |
| Changed / last seen | 2026-06-03 / 2026-06-06 |
Related slices
| Page | What it contains | Open |
|---|---|---|
| Company jobs | Active postings from FortifyIQ. | Open |
| Company breakdowns | Role, location, ATS, and work model facets for this company. | Open |
| ATS provider jobs | Active postings observed through Greenhouse. | Open |
| Provider filtered search | The same provider as a filtered job collection. | Open |
| Department jobs | Active postings in IT Support. | Open |
| Work model jobs | Active Remote postings. | Open |
| Lifecycle events | Open, update, close, and reopen events for this posting. | Open |
| Original posting | Canonical source or apply URL captured from the ATS. | Open |
Linked records
| Company | FortifyIQ |
| Source | 46d1a2af-70cf-4ada-aafe-ed8b714a27da |
| ATS provider | Greenhouse |
Description
We’re looking for a senior-level Hardware Design Engineer to take the lead on complex ASIC and FPGA development projects. This role blends architecture design, hands-on implementation, and technical leadership. You’ll collaborate across engineering teams to deliver high-performance, reliable silicon solutions in a flexible hybrid environment.
Responsibilities
Define HW architecture and evaluate design trade-offs for performance, area, and power.
Lead RTL development, integration, and verification throughout the design cycle.
Partner with firmware and verification teams to ensure top-quality silicon delivery.
Mentor and review junior engineers’ work, promoting best practices and technical excellence.
Provide design-in and bring-up support, including technical expertise for customer-facing projects.
Qualifications
Strong command of SystemVerilog for RTL design and digital architecture.
Experience using simulation tools such as Questa, Incisive, or VCS.
Skilled in scripting (Python, Perl, Tcl) for automation and workflow optimization.
Proven experience in ASIC or FPGA design, synthesis, and timing closure.
Strong analytical thinking and communication skills, with the ability to manage complex priorities.
10+ years of relevant experience and a BSEE or MSEE degree.
Preferred / Plus
Expertise in ASIC synthesis, timing constraints, CDC/RDC methodologies.
Familiarity with UVM-based verification environments.
Experience with high-speed memory technologies (HBM, GDDR, LPDDR, DDR).
Understanding of AMBA AXI or CHI protocols.
Full job record
| Job ID | 48402216e67f0dc8fe93576eb17f8933b3ce81e3 |
| Org ID | f4fabd70-af36-4304-86b9-4a5b4552bfe9 |
| Source ID | 46d1a2af-70cf-4ada-aafe-ed8b714a27da |
| Board ID | 46d1a2af-70cf-4ada-aafe-ed8b714a27da |
| Provider | greenhouse |
| Provider Job Key | 4661426005 |
| Title | Sr. Hardware Design Engineer (Remote) |
| Normalized Title | — |
| Status | active |
| Active | yes |
| Location Text | Remote |
| Department | IT Support |
| Team | — |
| Employment Type | — |
| Workplace Type | remote |
| Remote Policy | remote |
| Country | United States |
| Region | — |
| City | — |
| Salary Raw | — |
| Salary Min | — |
| Salary Max | — |
| Salary Currency | — |
| Salary Period | — |
| Source URL | https://job-boards.greenhouse.io/fortifyiq/jobs/4661426005 |
| Apply URL | https://job-boards.greenhouse.io/fortifyiq/jobs/4661426005 |
| First Seen At | 2026-05-29 22:58:18Z |
| Last Seen At | 2026-06-06 20:05:25Z |
| Last Checked At | 2026-06-06 20:05:25Z |
| Last Changed At | 2026-06-03 10:41:08Z |
| Inactive At | — |
| Source Posted At | 2026-02-12 19:25:54Z |
| Source Updated At | 2026-06-02 18:08:02Z |
| Raw Payload Uri | s3://job-postings-prod-raw-590183727216/raw/provider=greenhouse/board=fortifyiq/date=2026-06-06/2026-06-06T20-05-25-703Z-2d9e7d5c025ac8d16b41ad56d0b3d2cfda41ad437f80ec1bcdb5c1fd875bcac9.json |
Event Fields
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