Senior Principal ASIC FPGA Engineer

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    "description": "<h2>Basic Qualifications </h2>\n<p><strong>Education Requirements:</strong></p>\n<p>Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 10 years of relevant experience; or Master's degree plus a minimum of 8 years of relevant experience.</p>\n<p> </p>\n<p><strong>Clearance Requirements:</strong></p>\n<p> Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.</p>\n<h2>Responsibilities for this Position</h2>\n<p><strong>Duties and Tasks:</strong></p>\n<ul>\n <li>Responsible for definition, design, verification and documentation for ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array) developments</li>\n <li>Determines architecture, system simulation and detailed design approach</li>\n <li>Defines module interfaces and all aspects of device design and simulation</li>\n <li>Evaluates the process flow including but not limited to high level design, synthesis, place and route, timing and power utilization</li>\n <li>Creates test and simulation plans that establish functional criteria</li>\n <li>Verifies test results and analyzes performance</li>\n <li>May also review vendor capabilities, foundry technologies, device libraries and simulation tools</li>\n <li>May lead or have significant contributions to technical subcontract management for medium to large subcontracts that may include SOW development, proposal evaluation, source selection, technicaloversight, and subcontractor work product evaluation and acceptance</li>\n <li>Reviews vendor capability to support product development</li>\n <li>Applies an expert understanding of the organizationally defined processes throughout the lifecycle of the program or project</li>\n <li>Participates in the development, maintenance and improvement of the ASIC/FPGA organizational processes</li>\n <li>Supports the generation of technical engineering products by using the appropriate standards, processes, procedures, and tools throughout the development life cycle</li>\n <li>Leads the research and analysis of data, such as customer design proposal, specifications, and manuals to determine feasibility of design or application</li>\n <li>Selects components and equipment based on analysis of specifications and reliability</li>\n <li>May be a book boss on a medium proposal</li>\n <li>Establishes the overall ASIC/FPGA technical approach on large technical proposals</li>\n <li>May participate in multi-divisional or multi-company Integrated Product Team or working group</li>\n <li>May supervise or manage lower level employees</li>\n <li>Exercises considerable latitude in determining technical objectives of assignments</li>\n <li>Works on advanced applications that may result in new business for the company</li>\n</ul>\n<p> </p>\n<p><strong>Knowledge, Skills and Abilities:</strong></p>\n<ul>\n <li>Substantial use and understanding of ASIC/FPGA engineering concepts, principles, and theories </li>\n <li>Frequently contributes to the development of innovative principles and ideas </li>\n <li>Substantial understanding of company policies and practices </li>\n <li>Substantial understanding of ASIC/FPGA engineering processes </li>\n <li>Substantial awareness of business objectives and Engineering’s role in achieving </li>\n <li>Substantial proficiency in Microsoft Office applications </li>\n <li>Substantial written and verbal communications skills </li>\n <li>Ability to think creatively</li>\n <li>Ability to multi-task </li>\n <li>Substantial skill in communicating issues, impacts, and corrective actions </li>\n <li>Substantial ability to recognize and clearly report information relevant to sound engineering design</li>\n <li>Substantial understanding and ability to apply project leadership principles including SPI/CPI, Earned Value, Cost Account Management (CAM), and Statistical Process Controls</li>\n <li>Demonstrated ability to manage scope growth </li>\n <li>Frequent contact with all levels across the entire company </li>\n <li>Serves as consultant to management and customers on projects and applications </li>\n <li>May serve as company technical spokesperson </li>\n <li>Works under consultative direction on predetermined long-range objectives </li>\n <li>Assignments may be self-initiated </li>\n <li>Works on unusually complex problems and provides creative and innovative solutions</li>\n <li>May function in a Deputy Program Manager Engineering (DPME) role</li>\n <li>Identifies opportunities to apply AI for continuous improvement and innovation</li>\n</ul>\n<p> </p>\n<p>#LI-JH1</p>\n<p>#LI-Hybrid</p>\n<h2>Salary Note</h2>This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled.\n<h2>Combined Salary Range</h2>USD $191,146.00 - USD $212,053.00 /Yr.\n<h2>Company Overview</h2>\n<p>General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!</p>\n<p>Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans</p>",
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