Home › Companies › Datapelago › Sr. Compiler Engineer
Sr. Compiler Engineer
Datapelago · Mountain View, California, 94041, United States · Active · BambooHR
Job facts
| Field | Value |
|---|---|
| Company | Datapelago |
| Title | Sr. Compiler Engineer |
| Normalized title | - |
| Department / team | - |
| Location | Mountain View, United States |
| Work model | - |
| Employment type | Full Time |
| Salary | - |
| Status | active |
| ATS provider | BambooHR |
| Posted / first seen | 2025-10-28 / 2026-05-30 |
| Changed / last seen | 2026-05-30 / 2026-06-06 |
Related slices
| Page | What it contains | Open |
|---|---|---|
| Company jobs | Active postings from Datapelago. | Open |
| Company breakdowns | Role, location, ATS, and work model facets for this company. | Open |
| ATS provider jobs | Active postings observed through BambooHR. | Open |
| Provider filtered search | The same provider as a filtered job collection. | Open |
| City jobs | Active postings in Mountain View. | Open |
| Lifecycle events | Open, update, close, and reopen events for this posting. | Open |
| Original posting | Canonical source or apply URL captured from the ATS. | Open |
Linked records
| Company | Datapelago |
| Source | eaa6c882-d521-4b9b-a50a-5db329d4eb72 |
| ATS provider | BambooHR |
Description
Senior Compiler Engineer
Mountain View, CA
About DataPelago:
DataPelago is at the forefront of revolutionizing data processing for traditional analytics and cutting-edge GenAI preprocessing. We are building an innovative data processing engine that is transforming how Apache Spark, Apache Flink, Ray and others operate on diverse, large-scale data. Our team of engineers drive and adopt advances in hardware-accelerated computing, parallel processing of large-scale data, query optimization, distributed systems, compilers, machine learning, and cloud-native computing. We are looking for specialists to join our engineering team and shape the future of accelerated data processing.
The Opportunity:
As a Senior Compiler Engineer, you will lead the advancement of compilers for DataPelago’s data processing engine. You will enhance functional breadth, performance, scale, and reliability of DataPelago engine’s compilers in executing data processing workloads on diverse acceleration hardware infrastructure, including CPUs, GPUs. And FPGAs. This is a unique opportunity to make a significant impact on a category-defining product and work with a talented team of engineers.
What You'll Do:
• Architect: Lead the architecture of how our data processing engine will translate data processing logical and physical plans into efficient code for execution on CPU/GPU/FPGA.
• Design: Lead design of functional and performance enhancements to the compilers in our data processing engine.
• Core Development: Individually design, implement, test, optimize, and maintain components of compilers for the data processing engine.
• Innovation and Differentiation: Analyze advances in the capabilities of CPU and GPU processing elements from Nvidia, AMD, Intel, and others, compiler platforms and tools and identify opportunities for our engine to enhance technology and product leadership.
• Collaboration: Partner effectively with engineering and product management in defining language specifications of our product and ensuring compliance with industry standards, platform definitions, and workload requirements.
• Continuous Improvement: Foster best practices in design and code reviews, testing, CI/CD, and issue resolution to maintain highest product quality, security, efficiency, & productivity.
What You'll Bring:
• Bachelor's degree in Computer Science or a related field with 7+ years of relevant experience OR a Master's degree in Computer Science or a related field with 5+ years of relevant experience.
• 5+ years of deep technical experience in developing and enhancing production-quality com pilers, tools, or related software.
• Demonstrated experience with auto-vectorization compiler technologies and data-parallel architectures.
• Demonstrated experience with compiler internals. Solid experience with GCC/LLVM/ MLIR.
• Demonstrated experience with parsing, IR, type systems, and static analysis. Solid experience with flex/yacc/ANTLR.
• Experience with compilation for data applications (e.g., query compilers, query planners),
data processing languages (e.g., SQL, Python), acceleration hardware (e.g., Nvidia GPU),
and data processing engines (e.g., Apache Spark, Presto) preferred.
• Exceptional programming skills in C, C++. Rust experience preferred.
• Extensive development experience in Linux environments.
• Strong analytical and problem-solving skills with a passion for performance optimization.
Why Join DataPelago?
• Technology Leadership: Shape the architecture and development of how our core engine compiles parallel data processing applications on advanced acceleration hardware.
• Cutting-Edge Innovation: Work on challenging problems at the forefront of accelerated computing and data processing.
• Significant Impact: Your contributions will directly impact the performance and scalability of our mission-critical platform.
• Mentorship and Growth: Mentor and guide other talented engineers while expanding your own technical expertise.
• Competitive compensation, stock options, comprehensive benefits package, leadership development opportunities.
Full job record
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| Org ID | fad8cd3e-2f04-4a77-a77c-aeb512439968 |
| Source ID | eaa6c882-d521-4b9b-a50a-5db329d4eb72 |
| Board ID | eaa6c882-d521-4b9b-a50a-5db329d4eb72 |
| Provider | bamboohr |
| Provider Job Key | 48 |
| Title | Sr. Compiler Engineer |
| Normalized Title | — |
| Status | active |
| Active | yes |
| Location Text | Mountain View, California, 94041, United States |
| Department | — |
| Team | — |
| Employment Type | full_time |
| Workplace Type | — |
| Remote Policy | — |
| Country | United States |
| Region | — |
| City | Mountain View |
| Salary Raw | — |
| Salary Min | — |
| Salary Max | — |
| Salary Currency | — |
| Salary Period | — |
| Source URL | https://datapelago.bamboohr.com/careers/48 |
| Apply URL | https://datapelago.bamboohr.com/careers/48 |
| First Seen At | 2026-05-30 06:11:22Z |
| Last Seen At | 2026-06-06 10:26:05Z |
| Last Checked At | 2026-06-06 10:26:05Z |
| Last Changed At | 2026-05-30 06:11:22Z |
| Inactive At | — |
| Source Posted At | 2025-10-28 00:00:00Z |
| Source Updated At | — |
| Raw Payload Uri | s3://job-postings-prod-raw-590183727216/raw/provider=bamboohr/board=datapelago/date=2026-06-06/2026-06-06T10-26-04-697Z-7c727efe35d0e861fa42a8f6f2f986697f92d80acc804a198a3eef676d0d16da.json |
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"description": "<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; font-weight: bold\">Senior Compiler Engineer</span><br><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt\">Mountain View, CA</span></p>\n<p><br><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt; font-weight: bold\">About DataPelago:</span></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">DataPelago is at the forefront of revolutionizing data processing for traditional analytics and cutting-edge GenAI preprocessing. We are building an innovative data processing engine that is transforming how Apache Spark, Apache Flink, Ray and others operate on diverse, large-scale data. Our team of engineers drive and adopt advances in hardware-accelerated computing, parallel processing of large-scale data, query optimization, distributed systems, compilers, machine learning, and cloud-native computing. We are looking for specialists to join our engineering team and shape the future of accelerated data processing.</span></p>\n<p><br><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt; font-weight: bold\">The Opportunity:</span><br><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">As a Senior Compiler Engineer, you will lead the advancement of compilers for DataPelago’s data processing engine. You will enhance functional breadth, performance, scale, and reliability of DataPelago engine’s compilers in executing data processing workloads on diverse acceleration hardware infrastructure, including CPUs, GPUs. And FPGAs. This is a unique opportunity to make a significant impact on a category-defining product and work with a talented team of engineers.</span></p>\n<p><br></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt; font-weight: bold\">What You'll Do:</span></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">• Architect: Lead the architecture of how our data processing engine will translate data processing logical and physical plans into efficient code for execution on CPU/GPU/FPGA.</span></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">• Design: Lead design of functional and performance enhancements to the compilers in our </span><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">data processing engine.</span></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">• Core Development: Individually design, implement, test, optimize, and maintain components of compilers for the data processing engine.</span></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">• Innovation and Differentiation: Analyze advances in the capabilities of CPU and GPU processing elements from Nvidia, AMD, Intel, and others, compiler platforms and tools and </span><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">identify opportunities for our engine to enhance technology and product leadership.</span><br><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">• Collaboration: Partner effectively with engineering and product management in defining </span><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">language specifications of our product and ensuring compliance with industry standards, </span><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">platform definitions, and workload requirements.</span><br><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">• Continuous Improvement: Foster best practices in design and code reviews, testing, CI/CD, </span><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">and issue resolution to maintain highest product quality, security, efficiency, & productivity.</span></p>\n<p><br><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt; font-weight: bold\">What You'll Bring:</span></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">• Bachelor's degree in Computer Science or a related field with 7+ years of relevant experience OR a Master's degree in Computer Science or a related field with 5+ years of relevant </span><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">experience.</span></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">• 5+ years of deep technical experience in developing and enhancing production-quality com</span><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">pilers, tools, or related software.</span></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">• Demonstrated experience with auto-vectorization compiler technologies and data-parallel </span><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">architectures.</span></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">• Demonstrated experience with compiler internals. Solid experience with GCC/LLVM/ </span><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">MLIR.</span></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">• Demonstrated experience with parsing, IR, type systems, and static analysis. Solid experience with flex/yacc/ANTLR.</span></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">• Experience with compilation for data applications (e.g., query compilers, query planners),</span><br><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">data processing languages (e.g., SQL, Python), acceleration hardware (e.g., Nvidia GPU),</span><br><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">and data processing engines (e.g., Apache Spark, Presto) preferred.</span><br><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">• Exceptional programming skills in C, C++. Rust experience preferred.</span><br><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">• Extensive development experience in Linux environments.</span><br><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">• Strong analytical and problem-solving skills with a passion for performance optimization.</span></p>\n<p><br></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt; font-weight: bold\">Why Join DataPelago?</span><br><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">• Technology Leadership: Shape the architecture and development of how our core engine </span><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">compiles parallel data processing applications on advanced acceleration hardware.</span><br><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">• Cutting-Edge Innovation: Work on challenging problems at the forefront of accelerated </span><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">computing and data processing.</span><br><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">• Significant Impact: Your contributions will directly impact the performance and scalability </span><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">of our mission-critical platform.</span><br><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">• Mentorship and Growth: Mentor and guide other talented engineers while expanding your </span><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">own technical expertise.</span></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 10pt\">• Competitive compensation, stock options, comprehensive benefits package, leadership development opportunities.</span></p>",
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