PCB Layout Engineer - Avionics

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  "active_status": "active"
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    "city": "Saratoga",
    "region": "CA",
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  "remote_policy": null,
  "salary_period": "year",
  "workplace_type": "on_site",
  "salary_currency": "USD"
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{
  "lists": [
    {
      "text": "Key Responsibilities:",
      "content": "<ul style=\"margin-top: 0in; margin-bottom: 3.0pt;\">\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Develop PCB stack-ups for complex mixed-signal, power, and RF designs with appropriate impedance control.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Perform component placement optimized for signal integrity, thermal management, and manufacturability.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Route high-speed digital interfaces (SERDES, DDR, LVDS) with impedance-controlled transmission lines.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Implement power distribution plane design with attention to current density, loop area, and decoupling strategy.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Apply mixed-signal layout techniques with proper analog, digital, and RF isolation and partitioning.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Create and maintain footprint libraries and serve as Altium librarian for the program.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Manage design-rule and constraint creation including clearances, lengths, impedance targets, vias, and creepage/clearance requirements.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Produce layout documentation including fabrication drawings, assembly drawings, layer stack tables, and manufacturing notes.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Address RF parasitic effects through ground fencing, stitching vias, partitioning, and shielding techniques.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Coordinate with fabrication and assembly vendors for DFM reviews and manufacturing handoff.</li>\n</ul>"
    },
    {
      "text": "Required Qualifications:",
      "content": "\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Bachelor’s degree in Electrical Engineering, Electronic Engineering, or equivalent experience.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">5+ years of PCB layout experience for complex multi-layer boards (12+ layers).</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Proficiency with Altium Designer (strongly preferred) or equivalent PCB CAD tools (Allegro, Zuken).</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Demonstrated experience with impedance-controlled routing and high-speed signal layout.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Strong understanding of stack-up design for digital, power, and mixed-signal applications.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Experience creating fabrication packages (Gerbers, ODB++, drill files, assembly drawings).</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Knowledge of IPC standards and design-for-manufacture best practices.</li>\n"
    },
    {
      "text": "Preferred Qualifications:",
      "content": "<ul style=\"margin-top: 0in; margin-bottom: 3.0pt;\">\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Experience with aerospace or space-grade PCB layouts and qualification requirements.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Background in RF/microwave PCB layout including matching networks and transmission-line structures.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Familiarity with signal integrity and power integrity simulation tools (HyperLynx, Sigrity).</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Experience with Zuken CR-8000 or other enterprise PCB CAD tools.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Knowledge of high-speed signal attenuation, dispersion, and copper-loss mechanisms.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Experience with flex and rigid-flex PCB design.</li>\n</ul>"
    },
    {
      "text": "Tools & Technologies: ",
      "content": "<ul style=\"margin-top: 0in; margin-bottom: 3.0pt;\">\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Altium Designer (primary layout tool)</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Zuken CR-8000</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">HyperLynx (SI/PI review support)</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">ODB++ and CAM output tools</li>\n</ul>"
    }
  ],
  "country": "US",
  "createdAt": 1775170206748,
  "updatedAt": null,
  "categories": {
    "team": "Engineering & Operations",
    "location": "Saratoga, CA",
    "commitment": "Full-Time",
    "department": "E-Space US",
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