Lead Digital Verification Engineer

Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution We are looking for an experienced Design Verification Lead to drive the functional verification of complex SoC/IP designs from specification through tapeout in a newly formed hardware engineering organization. You will own the verification strategy, define methodology standards, build and guide a team of verification engineers, and serve as the final authority on verification quality and sign-off readiness. This role demands a strong blend of technical depth in modern verification methodologies (UVM, embedded C and compiler generated trace driven testing) and the leadership ability to execute across a multi-block chip program on schedul.e The DV Lead will help shape our internal processes for building robust and verified designs, including the company’s second product line, which will scale computing performance and capability, while improving energy efficiency. This is a unique opportunity to have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond! Key Responsibilities Define the end-to-end verification strategy across block, subsystem, and full-chip levels aligned with tapeout milestones Author and review verification plans mapping specifications to features, stimulus strategies(traditional stimulus generation, compiler driven), coverage goals, and sign-off criteria Architect scalable UVM-based testbench environments including agents, scoreboards, reference models, and coverage monitors Drive constrained-random stimulus development targeting protocol interactions, concurrency, error injection, and corner cases Define and close functional coverage models through systematic hole analysis, targeted tests, seed optimization, and regression tuning Deploy SystemVerilog Assertions for protocol compliance, interface checks, and design invariants across all simulation runs Lead full-chip verification including boot sequences, interrupt handling, DMA flows, power-on reset, and multi-block interactions Ensure CDC, RDC, and multi-power-domain verification in coordination with specialist tools and teams Debug complex simulation failures spanning multi-block interactions, protocol violations, race conditions, and timing-dependent corner cases Own the bug lifecycle — triage, prioritization, tracking, fix verification, and cross-functional resolution with RTL designers and architects Manage the regression framework — defining suites, maintaining stability, optimizing throughput, and integrating with CI/CD pipelines Coordinate simulation-to-emulation handoff ensuring verification collateral transitions effectively to emulation environments Collaborate cross-functionally with Compiler Team, RTL design, DFT, physical design, and post-silicon validation teams Lead, mentor, and grow the verification engineering team while maintaining a high quality bar through rigorous reviews Represent verification readiness in tapeout sign-off reviews and program-level decisions Support running gate-level simulations as part of design signoff. Assist in building a verification dashboard to quickly understand where a design is in the verification process and to identify regressions. Required Qualifications & Experience Education: Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field. Experience: 10+ years of progressive experience in ASIC/SoC design verification, with at least 3 years in a lead role owning verification strategy, sign-off, and team execution. UVM Mastery: Deep expertise in UVM-based testbench architecture and constrained-random verification methodology — not just usage, but architectural decision-making and optimization. SystemVerilog: Advanced proficiency in SystemVerilog for verification including classes, constraints, functional coverage, assertions (SVA), interfaces, and packages. Coverage Closure: Demonstrated track record of driving functional and code coverage to tapeout sign-off on complex, multi-million-gate SoC/ASIC designs. Debug Skills: Proven ability to debug deeply complex simulation failures spanning multiple design blocks, protocols, and abstraction levels. SoC Architecture: Strong understanding of modern SoC building blocks — processors (ARM, RISC-V), interconnects (AMBA AXI/ACE/CHI), memory controllers, DMA engines, interrupt controllers, and standard peripherals. Scripting & Automation: Proficiency in Python, Perl, or Tcl for test automation, log analysis, coverage post-processing, and regression flow development. Communication: Clear and effective communication of verification status, risk, and trade-offs to technical peers and program leadership. We offer a competitive salary for this role, generally ranging from $200,000 to $230,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate. Why Join Efficient? Efficient offers a competitive compensation and benefits package , including 401K match, company-paid benefits, equity program, paid parental leave, and flexibility . We are committed to personal and professional development and strive to grow together as people and as a company.

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