Principal Silicon Validation Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Overview: The mission of this role is to develop and execute electrical validation tests that quantify parametric device performance and operating margins across all system conditions. The validation team upholds customer requirements to the highest standard and serves as the final authority in certifying a product’s parametric compliance. Astera Labs is seeking motivated Principal / Senior Principal Post-Silicon Validation Engineers to support our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role, you will define comprehensive post-silicon validation plans, automate IC- and board-level testing, and design experiments to identify and root-cause unexpected behavior. You will analyze and report validation results against specifications, collaborate closely with key internal stakeholders, quantify performance margins, and ensure robust, production-ready designs. Basic Qualifications: Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred. ≥10 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for internal meetings in advance, and to work with minimal guidance and supervision. Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind! Proven track record solving problems independently, preferably as a tech lead Required experience Experience working on debug and bring-up of complicated SoC’s with high-speed interfaces such as PCIe/802.3 Ethernet Strong problem-solving skills, ability to solve problems independently Basic knowledge of key, high-speed design blocks such as PLL’s, CTLE, DFE, Tx EQ, PAM4 signaling Strong python scripting and coding ability: knowledge of object-oriented programming and basic dev ops using git for source control and collaboration Proficiency using high-speed lab equipment such as BERT, Oscilloscope, and VNA Preferred Experience: Experience in system testing, characterization, margin analysis and optimization of high-speed, multi-gigabit data links over long and short channels Familiarity with PCIe or Ethernet especially Electrical Compliance sections Hands-on experience with signal integrity, especially as it relates to PCIe/Ethernet testing and CEM/NVMe interfaces Working knowledge of C or C++ for embedded FW Familiarity with IEEE 802.3x Ethernet standards and both NRZ and PAM-4 signaling Working knowledge of common serial data specifications such as I2C, SPI, etc Knowledge of schematic capture and PCB layout tools from Cadence, Altium, etc. Knowledge of simulation tools such as MATLAB, Keysight ADS, or PLTS for data analysis and modeling of electrical channel and signal integrity issues The base salary range is USD 203,00 - USD 250,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

{
  "content_hash": "37d164395bf7fd2ef10c83cb14aa9078f28c1b2b9b8a8fe02bd80ab1a342eff9",
  "source_hash": "c24189b61c229f8eab148add5e520792c863d901773058ea187ce76585008165",
  "last_changed_at": "2026-06-06T07:35:38.727Z",
  "active_status": "active"
}

{
  "language": "en",
  "location": {
    "raw": "San Jose, CA",
    "city": "San Jose",
    "region": "CA",
    "country": "United States",
    "is_remote": false,
    "confidence": 0.9
  },
  "salary_max": null,
  "salary_min": null,
  "inferred_at": "2026-06-06T07:35:38.685Z",
  "launch_scope": {
    "reason": "english_us_canada",
    "included": true,
    "language": "en",
    "location": {
      "raw": "San Jose, CA",
      "city": "San Jose",
      "region": "CA",
      "country": "United States",
      "is_remote": false,
      "confidence": 0.9
    },
    "countries": [
      "United States"
    ]
  },
  "remote_policy": null,
  "salary_period": null,
  "workplace_type": null,
  "salary_currency": null
}

{}

{
  "title": "Principal Silicon Validation Engineer",
  "offices": [
    {
      "id": 4000118005,
      "name": "San Jose",
      "location": "San Jose, United States",
      "child_ids": [],
      "parent_id": 4019546005
    }
  ],
  "language": "en",
  "location": {
    "name": "San Jose, CA"
  },
  "metadata": [
    {
      "id": 12122734005,
      "name": "Country",
      "value": null,
      "value_type": "single_select"
    },
    {
      "id": 12122790005,
      "name": "City",
      "value": null,
      "value_type": "single_select"
    },
    {
      "id": 7826080005,
      "name": "Job Family/Domain",
      "value": "Hardware Engineering",
      "value_type": "single_select"
    },
    {
      "id": 7826085005,
      "name": "Role Type",
      "value": "Experienced",
      "value_type": "single_select"
    }
  ],
  "updated_at": "2026-06-05T13:07:16-04:00",
  "departments": [
    {
      "id": 4025526005,
      "name": "Hardware Engineering",
      "child_ids": [],
      "parent_id": 4000196005
    }
  ],
  "company_name": "Astera Labs",
  "requisition_id": 4397108005,
  "first_published": "2025-12-23T13:03:15-05:00",
  "application_deadline": null
}