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ASIC Design Verification Engineer

Avicena Tech, Corp. · Sunnyvale, CA, United States · On Site · Active · Rippling ATS

Job facts

FieldValue
CompanyAvicena Tech, Corp.
TitleASIC Design Verification Engineer
Normalized title-
Department / teamASIC development
LocationSunnyvale, CA, United States
Work modelOn Site
Employment typeFull Time
Salary-
Statusactive
ATS providerRippling ATS
Posted / first seen2025-10-03 / 2026-05-29
Changed / last seen2026-06-06 / 2026-06-06

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PageWhat it containsOpen
Company jobsActive postings from Avicena Tech, Corp..Open
Company breakdownsRole, location, ATS, and work model facets for this company.Open
ATS provider jobsActive postings observed through Rippling ATS.Open
Provider filtered searchThe same provider as a filtered job collection.Open
City jobsActive postings in Sunnyvale.Open
Department jobsActive postings in ASIC development.Open
Work model jobsActive On Site postings.Open
Lifecycle eventsOpen, update, close, and reopen events for this posting.Open
Original postingCanonical source or apply URL captured from the ATS.Open

Linked records

CompanyAvicena Tech, Corp.
Source975aa5ec-8f41-46cf-b409-2232313db55e
ATS providerRippling ATS

Description

company Avicena is a privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications.  This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace. Avicena is headquartered in Sunnyvale, California with a development center in Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry with a track record of delivering breakthrough products.  ( www.avicena.tech ) role About the role: Avicena is seeking a talented and detail-oriented ASIC Design Verification (DV) Engineer to join our chip design team. You'll play a crucial role in ensuring the functional correctness, performance, and robustness of our high-speed, low-power digital integrated circuits (ICs) for groundbreaking silicon photonics and optical interconnect solutions. This position requires strong expertise in verification methodology and a commitment to quality. Responsibilities: Testbench Development: Develop comprehensive and reusable verification environments (Testbenches) from scratch using advanced methodologies like UVM (Universal Verification Methodology). Verification Planning: Work closely with the architecture and design teams to define and execute thorough verification plans, including feature lists, test strategies, and coverage goals. Test Case Creation: Develop constrained-random, directed, and stress tests, as well as necessary sequences, scores, and functional coverage models. Functional Debugging: Execute simulations, analyze results, and effectively debug complex functional failures, working with design engineers to identify and resolve root causes. Coverage Closure: Drive functional and code coverage closure, identifying coverage holes and implementing targeted tests to achieve tape-out quality. Regression Management: Maintain and manage regression suites, optimizing simulation speed and efficiency. Formal Verification: Utilize formal verification techniques to prove correctness for critical design properties, such as clock domain crossing (CDC) and complex state machines. Scripting and Automation: Develop and maintain automation scripts (e.g., in Python or Perl) to enhance the verification flow and improve efficiency. Qualifications: Required: Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Experience: 3+ years of professional experience in ASIC/SoC design verification. UVM Expertise: Strong proficiency and hands-on experience in building and deploying reusable verification environments using SystemVerilog and UVM. Verification Languages: Expertise in SystemVerilog, and knowledge of scripting languages like Python or Perl. Tool Proficiency: Experience with industry-standard EDA simulation and debug tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa). Coverage Driven Methodology: Solid understanding of constrained-random verification and functional/code coverage analysis. Debugging Skills: Excellent analytical and problem-solving skills with a proven ability to debug complex digital logic and verification environments. Preferred (Nice to Have): Experience verifying high-speed interfaces, SerDes, or communication protocols like Ethernet and PCIe. Exposure to forward error correction (FEC), scrambling, and other digital data communication techniques. Knowledge of formal verification tools (e.g., Synopsys VC Formal, Cadence JasperGold). Familiarity with low-power verification techniques. Experience with hardware description languages (HDL) like Verilog/SystemVerilog for basic design understanding. Exposure to physical layer (PHY) or mixed-signal verification concepts.

Full job record

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Source ID975aa5ec-8f41-46cf-b409-2232313db55e
Board ID975aa5ec-8f41-46cf-b409-2232313db55e
Providerrippling
Provider Job Keyf9df189f-0608-46ef-8c26-4e7adde76215
TitleASIC Design Verification Engineer
Normalized Title—
Statusactive
Activeyes
Location TextSunnyvale, CA, United States
DepartmentASIC development
Team—
Employment Typefull_time
Workplace Typeon_site
Remote Policy—
CountryUnited States
RegionCA
CitySunnyvale
Salary Raw—
Salary Min—
Salary Max—
Salary Currency—
Salary Period—
Source URLhttps://ats.rippling.com/general/jobs/f9df189f-0608-46ef-8c26-4e7adde76215
Apply URLhttps://ats.rippling.com/general/jobs/f9df189f-0608-46ef-8c26-4e7adde76215
First Seen At2026-05-29 07:13:36Z
Last Seen At2026-06-06 08:45:46Z
Last Checked At2026-06-06 08:45:46Z
Last Changed At2026-06-06 08:45:46Z
Inactive At—
Source Posted At2025-10-03 23:40:28Z
Source Updated At—
Raw Payload Uris3://job-postings-prod-raw-590183727216/raw/provider=rippling/board=general/date=2026-06-06/2026-06-06T08-45-45-695Z-8efdc24749320309cc94abbcb3ddd9296d1225febbdcc3aaf07fee3eb4764109.json
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      "role": "<meta><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:0px;line-height:1.38;padding:0px;\"><br></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:18pt;font-weight:400;margin:0px;line-height:1.38;padding:0px;\"><b><strong style=\"font-size:18pt;white-space:pre-wrap;\">About the role:</strong></b></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:0px;line-height:1.38;padding:0px;\"><span style=\"white-space:pre-wrap;\">Avicena is seeking a talented and detail-oriented ASIC Design Verification (DV) Engineer to join our chip design team. You'll play a crucial role in ensuring the functional correctness, performance, and robustness of our high-speed, low-power digital integrated circuits (ICs) for groundbreaking silicon photonics and optical interconnect solutions. This position requires strong expertise in verification methodology and a commitment to quality.</span><span style=\"color:rgb(0,0,0);background-color:rgb(255,255,255);font-size:12pt;white-space:pre-wrap;\">&nbsp;</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:0px;line-height:1.38;padding:0px;\"><br></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:18pt;font-weight:400;margin:0px;line-height:1.38;padding:0px;\"><b><strong style=\"font-size:18pt;white-space:pre-wrap;\">Responsibilities:</strong></b></p><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:16px 0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"margin:0px;text-indent:0px;font-size:12pt;line-height:1.38;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Testbench Development: Develop comprehensive and reusable verification environments (Testbenches) from scratch using advanced methodologies like UVM (Universal Verification Methodology).&nbsp;</span></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:16px 0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"margin:0px;text-indent:0px;font-size:12pt;line-height:1.38;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Verification Planning: Work closely with the architecture and design teams to define and execute thorough verification plans, including feature lists, test strategies, and coverage goals.&nbsp;</span></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:16px 0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"margin:0px;text-indent:0px;font-size:12pt;line-height:1.38;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Test Case Creation: Develop constrained-random, directed, and stress tests, as well as necessary sequences, scores, and functional coverage models.&nbsp;</span></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:16px 0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"margin:0px;text-indent:0px;font-size:12pt;line-height:1.38;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Functional Debugging: Execute simulations, analyze results, and effectively debug complex functional failures, working with design engineers to identify and resolve root causes.&nbsp;</span></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:16px 0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"margin:0px;text-indent:0px;font-size:12pt;line-height:1.38;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Coverage Closure: Drive functional and code coverage closure, identifying coverage holes and implementing targeted tests to achieve tape-out quality.&nbsp;</span></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:16px 0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"margin:0px;text-indent:0px;font-size:12pt;line-height:1.38;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Regression Management: Maintain and manage regression suites, optimizing simulation speed and efficiency.&nbsp;</span></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:16px 0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"margin:0px;text-indent:0px;font-size:12pt;line-height:1.38;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Formal Verification: Utilize formal verification techniques to prove correctness for critical design properties, such as clock domain crossing (CDC) and complex state machines.&nbsp;</span></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:16px 0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"margin:0px;text-indent:0px;font-size:12pt;line-height:1.38;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Scripting and Automation: Develop and maintain automation scripts (e.g., in Python or Perl) to enhance the verification flow and improve efficiency.&nbsp;</span></li></ul><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:0px;line-height:1.38;padding:0px;\"><b><strong style=\"font-size:18pt;white-space:pre-wrap;\">Qualifications:</strong></b></p><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:16px 0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"margin:0px;text-indent:0px;font-size:12pt;line-height:1.38;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Required:&nbsp;</span></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:16px 0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:12pt;list-style:none;margin:0px;line-height:1.38;\"><ul data-pattern=\"discCircleSquare\" data-depth=\"2\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin-left:0px;margin-right:0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:circle;\"><li style=\"margin:0px;text-indent:0px;font-size:12pt;line-height:1.38;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.&nbsp;</span></li></ul></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:16px 0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:12pt;list-style:none;margin:0px;line-height:1.38;\"><ul data-pattern=\"discCircleSquare\" data-depth=\"2\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin-left:0px;margin-right:0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:circle;\"><li style=\"margin:0px;text-indent:0px;font-size:12pt;line-height:1.38;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Experience: 3+ years of professional experience in ASIC/SoC design verification.&nbsp;</span></li></ul></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:16px 0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:12pt;list-style:none;margin:0px;line-height:1.38;\"><ul data-pattern=\"discCircleSquare\" data-depth=\"2\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin-left:0px;margin-right:0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:circle;\"><li style=\"margin:0px;text-indent:0px;font-size:12pt;line-height:1.38;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">UVM Expertise: Strong proficiency and hands-on experience in building and deploying reusable verification environments using SystemVerilog and UVM.&nbsp;</span></li></ul></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:16px 0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:12pt;list-style:none;margin:0px;line-height:1.38;\"><ul data-pattern=\"discCircleSquare\" data-depth=\"2\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin-left:0px;margin-right:0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:circle;\"><li style=\"margin:0px;text-indent:0px;font-size:12pt;line-height:1.38;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Verification Languages: Expertise in SystemVerilog, and knowledge of scripting languages like Python or Perl.&nbsp;</span></li></ul></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:16px 0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:12pt;list-style:none;margin:0px;line-height:1.38;\"><ul data-pattern=\"discCircleSquare\" data-depth=\"2\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin-left:0px;margin-right:0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:circle;\"><li style=\"margin:0px;text-indent:0px;font-size:12pt;line-height:1.38;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Tool Proficiency: Experience with industry-standard EDA simulation and debug tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa).&nbsp;</span></li></ul></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:16px 0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:12pt;list-style:none;margin:0px;line-height:1.38;\"><ul data-pattern=\"discCircleSquare\" data-depth=\"2\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin-left:0px;margin-right:0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:circle;\"><li style=\"margin:0px;text-indent:0px;font-size:12pt;line-height:1.38;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Coverage Driven Methodology: Solid understanding of constrained-random verification and functional/code coverage analysis.&nbsp;</span></li></ul></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:16px 0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:12pt;list-style:none;margin:0px;line-height:1.38;\"><ul data-pattern=\"discCircleSquare\" data-depth=\"2\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin-left:0px;margin-right:0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:circle;\"><li style=\"margin:0px;text-indent:0px;font-size:12pt;line-height:1.38;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Debugging Skills: Excellent analytical and problem-solving skills with a proven ability to debug complex digital logic and verification environments.&nbsp;</span></li></ul></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:16px 0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"margin:0px;text-indent:0px;font-size:12pt;line-height:1.38;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Preferred (Nice to Have):&nbsp;</span></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:16px 0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:12pt;list-style:none;margin:0px;line-height:1.38;\"><ul data-pattern=\"discCircleSquare\" data-depth=\"2\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin-left:0px;margin-right:0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:circle;\"><li style=\"margin:0px;text-indent:0px;font-size:12pt;line-height:1.38;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Experience verifying high-speed interfaces, SerDes, or communication protocols like Ethernet and PCIe.&nbsp;</span></li></ul></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:16px 0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:12pt;list-style:none;margin:0px;line-height:1.38;\"><ul data-pattern=\"discCircleSquare\" data-depth=\"2\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin-left:0px;margin-right:0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:circle;\"><li style=\"margin:0px;text-indent:0px;font-size:12pt;line-height:1.38;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Exposure to forward error correction (FEC), scrambling, and other digital data communication techniques.&nbsp;</span></li></ul></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:16px 0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:12pt;list-style:none;margin:0px;line-height:1.38;\"><ul data-pattern=\"discCircleSquare\" data-depth=\"2\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin-left:0px;margin-right:0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:circle;\"><li style=\"margin:0px;text-indent:0px;font-size:12pt;line-height:1.38;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Knowledge of formal verification tools (e.g., Synopsys VC Formal, Cadence JasperGold).&nbsp;</span></li></ul></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:16px 0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:12pt;list-style:none;margin:0px;line-height:1.38;\"><ul data-pattern=\"discCircleSquare\" data-depth=\"2\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin-left:0px;margin-right:0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:circle;\"><li style=\"margin:0px;text-indent:0px;font-size:12pt;line-height:1.38;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Familiarity with low-power verification techniques.&nbsp;</span></li></ul></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:16px 0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:12pt;list-style:none;margin:0px;line-height:1.38;\"><ul data-pattern=\"discCircleSquare\" data-depth=\"2\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin-left:0px;margin-right:0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:circle;\"><li style=\"margin:0px;text-indent:0px;font-size:12pt;line-height:1.38;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Experience with hardware description languages (HDL) like Verilog/SystemVerilog for basic design understanding.&nbsp;</span></li></ul></li></ul><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:16px 0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:12pt;list-style:none;margin:0px;line-height:1.38;\"><ul data-pattern=\"discCircleSquare\" data-depth=\"2\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin-left:0px;margin-right:0px;line-height:1.38;padding:0px 0px 0px 32px;list-style-type:circle;\"><li style=\"margin:0px;text-indent:0px;font-size:12pt;line-height:1.38;\"><span style=\"font-size:12pt;white-space:pre-wrap;\">Exposure to physical layer (PHY) or mixed-signal verification concepts.&nbsp;</span></li></ul></li></ul>",
      "company": "<meta><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:0px;line-height:1.38;padding:0px;\"><b><strong style=\"font-size:11pt;white-space:pre-wrap;\">Avicena</strong></b><span style=\"font-size:11pt;white-space:pre-wrap;\">&nbsp;is a privately held company developing&nbsp;microLED&nbsp;based ultra-low power high bandwidth interconnects for chip-to-chip communications.  This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace.&nbsp;Avicena&nbsp;is headquartered in&nbsp;Sunnyvale, California with a development center in&nbsp;Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry with&nbsp;a track record&nbsp;of delivering breakthrough products.  (</span><a href=\"http://www.avicena.tech/\" target=\"_blank\" class=\"css-173makr-linkStyle\" style=\"color:rgb(71,102,159);cursor:pointer;\"><span style=\"white-space:pre-wrap;\">www.avicena.tech</span></a><span style=\"font-size:11pt;white-space:pre-wrap;\">) &nbsp;</span><span style=\"white-space:pre-wrap;\">&nbsp;</span></p>"
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GET https://api.bluedoor.sh/job-postings/v1/jobs/2d9f5ab67919fe0e4f35dcbaa02585b319ae765f?include=descriptionJSON
GET https://api.bluedoor.sh/job-postings/v1/orgs/c840fd90-50b5-48c0-b289-dffed50c1cc1JSON
GET https://api.bluedoor.sh/job-postings/v1/sources/975aa5ec-8f41-46cf-b409-2232313db55eJSON
GET https://api.bluedoor.sh/job-postings/v1/jobs/2d9f5ab67919fe0e4f35dcbaa02585b319ae765f/eventsJSON

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