Sr. Principal DSP Architect (Optical Transceivers & PAM4)

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview As a Sr. Principal DSP Architect, you will be the technical visionary leading the definition and development of next-generation Digital Signal Processing (DSP) architectures. Your focus will be on high-speed PAM4 (Pulse Amplitude Modulation 4-level) systems and coherent/direct-detect optical transceivers. You will bridge the gap between theoretical communications theory and silicon implementation, driving the roadmap for 800G, 1.6T, and beyond. Key Responsibilities Architectural Leadership: Lead the definition of DSP micro-architecture for high-performance ASICs, focusing on low-power, high-throughput data paths. Algorithm Development: Design, model, and simulate advanced DSP algorithms for: Adaptive Equalization (FFE, DFE, MLSE). Forward Error Correction (FEC). Clock and Data Recovery (CDR). Chromatic Dispersion (CD) and Polarization Mode Dispersion (PMD) compensation. Modeling & Simulation: Develop bit-accurate and performance-accurate models using Python, MATLAB, or C++ to validate architectural choices against Bit Error Rate (BER) targets. Cross-Functional Collaboration: Work closely with Analog Mixed-Signal (AMS) designers to optimize the ADC/DAC interface and with RTL teams to ensure power-efficient hardware implementation. Performance Trade-offs: Conduct rigorous Power, Performance, and Area (PPA) analysis to balance complex DSP requirements with the thermal and size constraints of optical modules (e.g., QSFP-DD, OSFP). Standards Contribution: Represent the company in industry standards bodies (IEEE 802.3, OIF) to influence future optical communications protocols. Required Qualifications Education: PhD or MS in Electrical Engineering, Communication Theory, or a related field. Experience: 12+ years of experience in DSP design, specifically for high-speed SerDes or optical communications. Technical Deep Dive: Expertise in PAM4 signaling and the associated challenges (non-linearity, SNR requirements). Deep understanding of Digital Filter Design (FIR, IIR) and adaptive signal processing. Experience with high-speed ADC/DAC architectures and their impact on DSP performance. Tooling: Proficiency in MATLAB/Simulink, Python (NumPy/SciPy), and SystemC. Silicon Success: A proven track record of taking complex DSP architectures from concept through tape-out to high-volume production. Preferred Skills Experience with Coherent Optical technologies (QAM, polarization multiplexing). Knowledge of Machine Learning applications in DSP for non-linearity compensation. Familiarity with hardware description languages (Verilog/SystemVerilog) and the synthesis flow The base salary range is $210,000 USD – $260,000 USD. Your base salary will be determined based on location, experience, and employees' pay in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

{
  "content_hash": "bb4559cdd4948b10d5e900223efecca0691b0f2367974a807ed0b9747aca6495",
  "source_hash": "07c46d3b00122af279eefe8810210b59277495bc10509961ab475a7f5c3f4f52",
  "last_changed_at": "2026-06-06T07:35:38.727Z",
  "active_status": "active"
}

{
  "language": "en",
  "location": {
    "raw": "San Jose, CA",
    "city": "San Jose",
    "region": "CA",
    "country": "United States",
    "is_remote": false,
    "confidence": 0.9
  },
  "salary_max": 260000,
  "salary_min": 210000,
  "inferred_at": "2026-06-06T07:35:38.717Z",
  "launch_scope": {
    "reason": "english_us_canada",
    "included": true,
    "language": "en",
    "location": {
      "raw": "San Jose, CA",
      "city": "San Jose",
      "region": "CA",
      "country": "United States",
      "is_remote": false,
      "confidence": 0.9
    },
    "countries": [
      "United States"
    ]
  },
  "remote_policy": null,
  "salary_period": "year",
  "workplace_type": null,
  "salary_currency": "USD"
}

{}

{
  "title": "Sr. Principal DSP Architect (Optical Transceivers & PAM4)",
  "offices": [
    {
      "id": 4000118005,
      "name": "San Jose",
      "location": "San Jose, United States",
      "child_ids": [],
      "parent_id": 4019546005
    }
  ],
  "language": "en",
  "location": {
    "name": "San Jose, CA"
  },
  "metadata": [
    {
      "id": 12122734005,
      "name": "Country",
      "value": null,
      "value_type": "single_select"
    },
    {
      "id": 12122790005,
      "name": "City",
      "value": null,
      "value_type": "single_select"
    },
    {
      "id": 7826080005,
      "name": "Job Family/Domain",
      "value": "Analog/Mixed-Signal",
      "value_type": "single_select"
    },
    {
      "id": 7826085005,
      "name": "Role Type",
      "value": "Experienced",
      "value_type": "single_select"
    }
  ],
  "updated_at": "2026-06-05T13:07:16-04:00",
  "departments": [
    {
      "id": 4135671005,
      "name": "SerDes",
      "child_ids": [],
      "parent_id": 4000196005
    }
  ],
  "company_name": "Astera Labs",
  "requisition_id": 4415582005,
  "first_published": "2026-01-26T15:46:20-05:00",
  "application_deadline": null
}