Senior FPGA Engineer

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          "text": "<p>Seeking an FPGA Engineer who has extensive knowledge of digital circuit design, state machines, Boolean math and FPGAs.</p><p>Candidate shall have experience with</p><ul><li>Completing multiple FPGA or ASIC design using Verilog and/or VHDL, including at least one of moderate complexity</li><li>Demonstrate knowledge and development of a test bench with self-checking and simulation (including back annotated timing) for given FPGA modules, top level FPGA, and system with multiple FPGAs</li><li>FPGA technology differences (Xilinx vs Actel/Microsemi)</li><li>FPGA process and development flows, especially flows using Synplify Pro, ISE, Vivado and Libero</li><li>Scripting languages such as TCL or Python</li><li>Leading small sized teams in order to develop moderately complex systems according to program schedule expectations</li></ul><p>Required skills</p><ul><li>FPGA design experience including thorough design documentation, completion and review of RTL blocks, participation in code reviews, significant RTL debug, and working knowledge of CDC, reset and clock design&#xa0;</li><li>Ability to solve digital lab debug problems with use of lab tools such as bench supplies, scopes and logic analyzers&#xa0;</li></ul><p>Knowledge of RTL design techniques for radiation upset mitigation and experience using multiple RTL languages&#xa0;are a plus.</p>",
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