Principal Analog ASIC Design Engineer

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  "detail": {
    "url": "https://xanadu.applytojob.com/apply/jobs/details/amWiAVnwXz?&",
    "heading": "Principal Analog ASIC Design Engineer",
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    "description_html": "<div class=\"job_description\">\n\t\t\t\t\t<p style=\"line-height:1.38;margin-top:16px;margin-bottom:16px;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:700;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">About Xanadu:</span></span></span></span></span><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">&#160;</span></span></span></span></span></span></span></p><p style=\"line-height:1.38;margin-top:16px;margin-bottom:16px;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Xanadu&#8217;s mission is to build quantum computers that are useful and available to people everywhere.</span></span></span></span></span></span></span></p><p style=\"line-height:1.38;margin-top:16px;margin-bottom:16px;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">At Xanadu, we are learners, innovators, researchers, collaborators and problem solvers. We are creating something that has never been built before. What we are doing is extremely hard, the classic moon shot. Few people in their life will be able to be a part of something like this, where if we are successful, the technologies we develop will solve some of the world&#8217;s most challenging problems and literally change the world. And that is something to be excited about!</span></span></span></span></span></span></span></p><p style=\"line-height:1.38;margin-top:16px;margin-bottom:16px;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:700;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Your role and responsibilities:</span></span></span></span></span><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">&#160;</span></span></span></span></span></span></span></p><p style=\"line-height:1.38;margin-top:16px;margin-bottom:16px;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">We are looking for an experienced and driven ASIC Engineer to join our hardware team and contribute to the development of cutting-edge photonic quantum computing systems. If you thrive on tackling complex challenges at the intersection of high-speed analog, high voltage, and advanced semiconductor technologies, we want to hear from you!</span></span></span></span></span></span></span></p><p style=\"line-height:1.38;margin-top:16px;margin-bottom:16px;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">This isn't your typical analog design job. We are building state-of-the-art photonic quantum computers, and this role is critical to controlling and reading out our core hardware. As our </span></span></span></span></span><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:700;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Principal Analog ASIC Design Engineer</span></span></span></span></span><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">, you will define the architectural roadmap and own the entire lifecycle of custom ASICs built to operate in truly demanding environments. You will be solving unique, industry-first challenges at the intersection of high-speed (&lt;10ns) and high-voltage (up to 100V) design. Critical blocks in the circuits you design and oversee will include ultra-low-noise transimpedance amplifiers and high-voltage amplifiers and drivers.</span></span></span></span></span></span></span></p><p style=\"line-height:1.38;margin-top:16px;margin-bottom:16px;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:700;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Key Responsibilities:</span></span></span></span></span></span></span></p><ul><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:700;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Architecture &amp; Strategy:</span></span></span></span></span><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\"> Define the technical roadmap, architectural specifications, and methodology for novel, high-performance analog and mixed-signal ASICs to meet next-generation quantum computing targets.</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:700;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Vendor &amp; Partner Management:</span></span></span></span></span><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\"> Serve as the primary technical interface with tier-1 external ASIC design houses, guide them through process surveys, preliminary simulations, detailed design, and ultimately, tape-out execution.</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:700;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Internal Design Ownership &amp; Tape-Out:</span></span></span></span></span><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\"> Lead the design, top-level layout integration, and verification strategy for complex tapeouts, ensuring first-time-right silicon success for critical system blocks.</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:700;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Testing, Characterization &amp; Debug:</span></span></span></span></span><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\"> Oversee advanced lab characterization strategies, analyzing silicon performance against complex system requirements and driving the resolution of deep technical anomalies.</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:700;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Cross-Functional &amp; Strategic Collaboration:</span></span></span></span></span><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\"> Partner closely with photonics, packaging, and systems architecture teams to co-design and solve foundational system-level integration and scalability challenges.</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:700;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Technical Leadership:</span></span></span></span></span><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\"> Mentor senior engineering staff, champion design best practices, and serve as the company-wide subject matter expert for analog IC design.</span></span></span></span></span></span></span></li></ul><p style=\"line-height:1.38;margin-top:16px;margin-bottom:16px;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:700;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Basic qualifications and experience:</span></span></span></span></span></span></span></p><ul><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:700;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Experience:</span></span></span></span></span><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\"> 10+ years of professional experience in analog or mixed-signal ASIC/IC design, with a history of leading successful complex IC projects.</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:700;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Full-Cycle Leadership:</span></span></span></span></span><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\"> A proven track record of steering multiple complex tapeouts from initial architecture definition through to successful silicon validation and system integration.</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:700;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Technical Mastery:</span></span></span></span></span><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\"> Deep experience in designing highly challenging analog circuits simultaneously constrained by both high-speed (e.g., &lt;10ns) AND high-voltage (e.g., 50V-100V) requirements.</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:700;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Process Versatility:</span></span></span></span></span><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\"> Extensive design experience across multiple advanced semiconductor process nodes (e.g., BCD, SOI, GaN, BiCMOS) and the ability to strategically select the optimal process for quantum applications.</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:700;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Tool Proficiency:</span></span></span></span></span><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\"> Mastery of industry-standard EDA environments (Cadence strongly preferred) along with the ability to define simulation and verification methodologies.</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:700;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Education:</span></span></span></span></span><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\"> A Bachelor's or Master's degree in Electrical Engineering or a related field with a focus on IC design.</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:700;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Communication:</span></span></span></span></span><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\"> Exceptional ability to synthesize complex technical concepts into clear documentation, design reviews, and strategic recommendations for both technical and non-technical stakeholders.</span></span></span></span></span></span></span></li></ul><p style=\"line-height:1.38;margin-top:16px;margin-bottom:16px;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:700;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Preferred qualifications and experience:</span></span></span></span></span></span></span></p><ul><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:700;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Photonics Experience:</span></span></span></span></span><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\"> Direct experience architecting interface electronics for photodetectors, optical modulators, or co-packaged optics.</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:700;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Advanced Processes:</span></span></span></span></span><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\"> Pioneer-level experience with High-Voltage SOI, RF Analog, or GaN process development and modeling.</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:700;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Advanced Education:</span></span></span></span></span><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\"> A Ph.D. focused on a relevant IC design topic.</span></span></span></span></span></span></span></li><li style=\"list-style-type:disc;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:700;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">Data Converters:</span></span></span></span></span><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#000000;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\"> Demonstrated experience architecting and delivering high-performance, custom DAC/ADC architectures.</span></span></span></span></span></span></span></li></ul><p style=\"line-height:1.38;\"><span style=\"font-size:14px;\"><span style=\"font-family:Arial, Helvetica, sans-serif;\"><span style=\"font-variant:normal;white-space:pre-wrap;\"><span style=\"color:#2b333a;\"><span style=\"background-color:#ffffff;\"><span style=\"font-weight:400;\"><span style=\"font-style:normal;\"><span style=\"text-decoration:none;\">This is for a new position. Your base salary will be determined based on your location, experience, and internal benchmarks. You will also be eligible for equity and benefits.</span></span></span></span></span></span></span></span></p><p> </p>\n\n<p><span style=\"font-size:12px\"><span style=\"font-family:Arial,Helvetica,sans-serif\">Our values are important. They are fundamental and lay the foundation for culture at Xanadu. Learn more about our values <a href=\"https://www.xanadu.ai/values\">here</a>.</span></span></p>\n\n<p><span style=\"font-size:12px\"><span style=\"font-family:Arial,Helvetica,sans-serif\">We are an equal opportunity employer and encourage candidates of all backgrounds to apply. We are committed to building an inclusive, safe, and equitable culture and fostering an environment where our employees feel included, valued, and heard. We are committed to meeting the needs of all individuals and support a barrier-free workplace. Should you require accommodations at any point during the recruitment process please contact Recruiting at <a href=\"/cdn-cgi/l/email-protection#582a3d3b2a2d312c31363f7e7b6e6c63203936393c2d763931\">recruiting&#64;xanadu.ai</a>. </span></span></p>\n\n<p><span style=\"font-size:12px\"><span style=\"font-family:Arial,Helvetica,sans-serif\">Please be advised that we may use artificial intelligence (AI) tools to assist in the screening and assessment of applicants for this position. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.</span></span></p>",
    "description_text": "About Xanadu:\n Xanadu’s mission is to build quantum computers that are useful and available to people everywhere.\n At Xanadu, we are learners, innovators, researchers, collaborators and problem solvers. We are creating something that has never been built before. What we are doing is extremely hard, the classic moon shot. Few people in their life will be able to be a part of something like this, where if we are successful, the technologies we develop will solve some of the world’s most challenging problems and literally change the world. And that is something to be excited about!\n Your role and responsibilities:\n We are looking for an experienced and driven ASIC Engineer to join our hardware team and contribute to the development of cutting-edge photonic quantum computing systems. If you thrive on tackling complex challenges at the intersection of high-speed analog, high voltage, and advanced semiconductor technologies, we want to hear from you!\n This isn't your typical analog design job. We are building state-of-the-art photonic quantum computers, and this role is critical to controlling and reading out our core hardware. As our Principal Analog ASIC Design Engineer , you will define the architectural roadmap and own the entire lifecycle of custom ASICs built to operate in truly demanding environments. You will be solving unique, industry-first challenges at the intersection of high-speed (\n Key Responsibilities:\n Architecture & Strategy: Define the technical roadmap, architectural specifications, and methodology for novel, high-performance analog and mixed-signal ASICs to meet next-generation quantum computing targets.\n Vendor & Partner Management: Serve as the primary technical interface with tier-1 external ASIC design houses, guide them through process surveys, preliminary simulations, detailed design, and ultimately, tape-out execution.\n Internal Design Ownership & Tape-Out: Lead the design, top-level layout integration, and verification strategy for complex tapeouts, ensuring first-time-right silicon success for critical system blocks.\n Testing, Characterization & Debug: Oversee advanced lab characterization strategies, analyzing silicon performance against complex system requirements and driving the resolution of deep technical anomalies.\n Cross-Functional & Strategic Collaboration: Partner closely with photonics, packaging, and systems architecture teams to co-design and solve foundational system-level integration and scalability challenges.\n Technical Leadership: Mentor senior engineering staff, champion design best practices, and serve as the company-wide subject matter expert for analog IC design.\n Basic qualifications and experience:\n Experience: 10+ years of professional experience in analog or mixed-signal ASIC/IC design, with a history of leading successful complex IC projects.\n Full-Cycle Leadership: A proven track record of steering multiple complex tapeouts from initial architecture definition through to successful silicon validation and system integration.\n Technical Mastery: Deep experience in designing highly challenging analog circuits simultaneously constrained by both high-speed (e.g.,\n Process Versatility: Extensive design experience across multiple advanced semiconductor process nodes (e.g., BCD, SOI, GaN, BiCMOS) and the ability to strategically select the optimal process for quantum applications.\n Tool Proficiency: Mastery of industry-standard EDA environments (Cadence strongly preferred) along with the ability to define simulation and verification methodologies.\n Education: A Bachelor's or Master's degree in Electrical Engineering or a related field with a focus on IC design.\n Communication: Exceptional ability to synthesize complex technical concepts into clear documentation, design reviews, and strategic recommendations for both technical and non-technical stakeholders.\n Preferred qualifications and experience:\n Photonics Experience: Direct experience architecting interface electronics for photodetectors, optical modulators, or co-packaged optics.\n Advanced Processes: Pioneer-level experience with High-Voltage SOI, RF Analog, or GaN process development and modeling.\n Advanced Education: A Ph.D. focused on a relevant IC design topic.\n Data Converters: Demonstrated experience architecting and delivering high-performance, custom DAC/ADC architectures.\n This is for a new position. Your base salary will be determined based on your location, experience, and internal benchmarks. You will also be eligible for equity and benefits.\n Our values are important. They are fundamental and lay the foundation for culture at Xanadu. Learn more about our values here .\n We are an equal opportunity employer and encourage candidates of all backgrounds to apply. We are committed to building an inclusive, safe, and equitable culture and fostering an environment where our employees feel included, valued, and heard. We are committed to meeting the needs of all individuals and support a barrier-free workplace. Should you require accommodations at any point during the recruitment process please contact Recruiting at [email protected] .\n Please be advised that we may use artificial intelligence (AI) tools to assist in the screening and assessment of applicants for this position. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.",
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    "id": "amWiAVnwXz",
    "title": "Principal Analog ASIC Design Engineer",
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