Silicon Photonics Layout Designer

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    "description": "<p><span style=\"font-size: 14pt; font-weight: bold\"><span>About Us</span></span><span> </span></p>\n<p><span><span>Ranovus</span><span> is</span></span><span><span> a semiconductor company with </span></span><span><span>global operations</span></span><span><span> helping power the data behind next</span></span><span><span> </span></span><span><span>generation AI and data center networks. We design and build advanced hardware that moves massive amounts of information quickly and efficiently between computer systems in data centers around the world. Our technology improves performance while reducing energy use and environmental impact, supporting the rapid growth of AI and cloud services. At </span><span>Ranovus</span><span>, </span><span>you’ll</span><span> join a collaborative, inclusive team that values learning, flexibility, and meaningful work with global impact.</span></span><span> </span></p>\n<p><br></p>\n<p><span style=\"font-weight: bold\"><span style=\"font-size: 14pt; font-weight: bold\">The Opportunity</span><span style=\"font-size: 10pt\"> </span></span></p>\n<p>We are seeking a Full Time Silicon Photonics Layout Designer to develop high-quality physical layouts for advanced photonic integrated circuits. The ideal candidate has strong experience using Cadence layout tools and a solid understanding of LVS/DRC flows for photonic designs. You will work closely with photonic device engineers, circuit designers, and process teams to translate schematics and specifications into manufacturable layouts for silicon photonics platforms.</p>\n<p><br></p>\n<p><span style=\"font-weight: bold\"><span style=\"font-size: 14pt; font-weight: bold\">How You’ll Contribute</span><span style=\"font-size: 10pt\"> </span></span></p>\n<ul>\n<li>Create and maintain photonic layouts using Cadence (Virtuoso) and foundry PDKs.</li>\n<li>Implement waveguide routing, passive and electro-optic devices (rings, MZIs, couplers, modulators, detectors).</li>\n<li>Ensure layout compliance with foundry design rules (DRC) and perform LVS between schematic and layout.</li>\n<li>Debug and resolve DRC/LVS issues, including photonic-specific connectivity and hierarchy challenges.</li>\n<li>Integrate optical and electrical components in compact, manufacturable floorplans.</li>\n<li>Collaborate with design, modeling, and process teams to optimize layouts for performance, yield, and reliability.</li>\n<li>Prepare tape-out-ready GDS files and support signoff flows.</li>\n<li>Develop and improve layout methodologies, templates, and automation where applicable.</li>\n<li>Document layout guidelines and contribute to best practices for PIC design.</li>\n</ul>\n<p><br></p>\n<p><span style=\"font-size: 14pt; font-weight: bold\"><span style=\"font-weight: bold\">What You’ll Bring</span><span> </span></span></p>\n<ul>\n<li>Bachelor’s or master’s degree in electrical engineering, Photonics, Physics, or a related field.</li>\n<li>3+ years of experience in IC or photonic layout design.</li>\n<li>Strong proficiency with Cadence Virtuoso for layout.</li>\n<li>Hands-on experience running and debugging DRC and LVS.</li>\n<li>Familiarity with silicon photonics components and layouts (waveguides, rings, MZIs, grating couplers, heaters, PN junctions).</li>\n<li>Understanding of hierarchical layout, parameterized cells (PCells), and foundry PDK usage.</li>\n<li>Experience with mixed photonic/electrical layouts is a plus.</li>\n<li>Ability to interpret schematics, netlists, and design specifications.</li>\n<li>Strong attention to detail and ability to manage complex layouts across large designs.</li>\n</ul>\n<p><br></p>\n<p><span style=\"font-weight: bold\">Nice to Have</span></p>\n<ul>\n<li>Experience with photonic LVS frameworks or custom connectivity checks.</li>\n<li>Scripting experience (Python, SKILL, MATLAB) for layout automation.</li>\n<li>Familiarity with multiple foundries or photonics PDKs (e.g., GF, TSMC, IME, Tower Jazz).</li>\n<li>Experience supporting silicon photonics tape-outs and post-silicon debug.</li>\n</ul>\n<p><br></p>\n<p>We appreciate the time you invest in exploring opportunities with us. At Ranovus, we believe diverse perspectives and a strong sense of belonging are essential to building innovative technology and resilient teams. If your experience does not match every requirement, we still encourage you to apply. We value curiosity, growth, and the unique strengths each person brings.</p>\n<p><br></p>\n<p>Ranovus is an equal opportunity employer and welcomes applicants from all backgrounds and lived experiences, including those from equity deserving and underrepresented communities. We are committed to an accessible recruitment process in accordance with the Accessibility for Ontarians with Disabilities Act. Accommodations are available at any stage of the hiring process upon request by reaching out to our Talent team at <a href=\"mailto:[email protected]\" target=\"_blank\" rel=\"noopener noreferrer\">[email protected]</a>.</p>\n<p><br></p>\n<p>We are committed to delivering a respectful and transparent candidate experience, with clear and timely communication at every stage of the process. From time to time, we may use technology to support elements of our hiring process. These tools are designed to enhance consistency and efficiency, not replace human judgment. All hiring decisions are made by people, guided by care, context, and fairness.</p>\n<p><br></p>\n<p>Thank you for your interest in joining Ranovus. We look forward to connecting with you.</p>",
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