Digital Verification Engineers - 7 openings

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    "description": "<p><span style=\"font-size: 12pt\">At<span> </span><span style=\"font-weight: bold\">Kandou</span>, we are redefining the economics of AI infrastructure. Our mission is to<span> </span><span style=\"font-weight: bold\">democratise AI by significantly reducing the Total Cost of Ownership (TCO)<span> </span></span>of hardware systems — a critical barrier to scalable adoption.</span></p>\n<p><br></p>\n<p><span style=\"font-size: 12pt\">Our proprietary <span style=\"font-weight: bold\">MIMO-over-copper technology<span> </span></span>powers a<span> </span><span style=\"font-weight: bold\">high-performance, chiplet-based AI memory fabric<span> </span></span>that is both<span> </span><span style=\"font-weight: bold\">scalable and energy-efficient</span>. Unlike traditional interconnects, our solution<span> </span><span style=\"font-weight: bold\">reduces power consumption significantly<span> </span></span>while preserving<span> </span><span style=\"font-weight: bold\">high bandwidth and ultra-low latency<span> </span></span>— unlocking unprecedented efficiency for AI training and inference at scale.</span></p>\n<p><br></p>\n<p><span style=\"font-size: 12pt\">Kandou’s architecture is not just an incremental improvement — it’s a <span style=\"font-weight: bold\">foundational shift<span> </span></span>in how AI hardware is built for the future.</span></p>\n<p><br></p>\n<p><span>Job Title: <span style=\"font-weight: bold\">Digital Verification Engineer</span></span></p>\n<p><span>Location: </span><span style=\"font-weight: bold\">Hyderabad OR Bangalore</span></p>\n<p><br></p>\n<p><span style=\"font-weight: bold\">Key Responsibilities</span></p>\n<ul>\n<li>Develop design verification methodologies and implement standard debug flows</li>\n</ul>\n<ul>\n<li>Work with designers in verification and validation of circuit designs</li>\n</ul>\n<ul>\n<li>Participate in design reviews</li>\n</ul>\n<ul>\n<li>Prepare design verification plan based on design specifications</li>\n</ul>\n<ul>\n<li>Plan and schedule assigned projects for timely completion</li>\n</ul>\n<ul>\n<li>Utilize the latest techniques, tools, and technologies for design verification activities</li>\n</ul>\n<ul>\n<li>Maintain design verification environment and track &amp; close design bugs</li>\n</ul>\n<p><br></p>\n<p><span style=\"font-weight: bold\">Skills</span></p>\n<ul>\n<li>Must possess great communication skills, rigorous with an analytical mind and be a strong team player</li>\n</ul>\n<ul>\n<li>Good scripting techniques, regression setup &amp; management </li>\n</ul>\n<ul>\n<li>Deep understanding of simulation and verification environments</li>\n</ul>\n<ul>\n<li>Strong knowledge on Metrics-driven verification (incl. test planning and coverage closure)</li>\n</ul>\n<ul>\n<li>Deep knowledge of simulations tools and debugging techniques</li>\n</ul>\n<ul>\n<li>Understanding of verification planning and test bench development using the latest methodologies</li>\n</ul>\n<ul>\n<li>Experience with 3rd party VIP usage and test development (a big plus)</li>\n</ul>\n<ul>\n<li>Experience with Assertion Based Verification (a big plus)</li>\n</ul>\n<p><br></p>\n<p><span style=\"font-weight: bold\">Experience</span></p>\n<ul>\n<li>5+ years’ experience in the semiconductor industry</li>\n</ul>\n<ul>\n<li>Proven track record in verifying complex designs (preferably in high volume applications) - FPGA or ASIC</li>\n</ul>\n<ul>\n<li>Skilled in trade-offs between quality and schedule</li>\n</ul>\n<ul>\n<li>Experience in constrained random test bench development</li>\n<li>Familiarity with SerDes and high-level protocols (e.g., PCle, USB, DP) would be advantageous</li>\n</ul>\n<ul>\n<li>Extensive digital verification background with some UVM experience</li>\n</ul>\n<p><br></p>\n<p><span style=\"font-weight: bold\">Education</span></p>\n<p>Bachelor of Engineering in Electronics and Electrical Engineer (equivalent or higher)</p>\n<p><br></p>\n<p><span style=\"color: rgb(29, 34, 40); font-family: 'Inter', sans-serif; font-size: 12pt\">If this is the role you have been looking for and you want to be part of a growing Company, with an exciting future then we would really love to hear from you. Together We Kandou It !</span></p>\n<p><span style=\"color: rgb(29, 34, 40); font-family: 'Inter', sans-serif; font-size: 12pt\"><br></span></p>\n<p><span style=\"font-family: arial, helvetica, sans-serif\"><span><span style=\"font-family: 'Inter', sans-serif\"><span style=\"color: rgb(34, 34, 34)\">Visit us at </span><a href=\"https://www.kandou.ai/\" target=\"_blank\" rel=\"noopener noreferrer\">www.kandou.ai</a><span style=\"color: rgb(34, 34, 34)\"> and </span></span><a href=\"https://www.linkedin.com/company/kandou-ai/posts?lipi=urn%3Ali%3Apage%3Acompanies_company_index%3Bd9883c75-e180-4084-9488-1a503e730cfe\" target=\"_blank\" rel=\"noopener noreferrer\"><span style=\"font-family: 'Inter', sans-serif\">https://www.linkedin.com/company/kandou-ai/</span></a></span></span></p>\n<p><br><br></p>",
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