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IP Logic Design Engineer

Solidigm · Rancho Cordova, , United States · Active · $105,440–$164,800 / year · SmartRecruiters

Job facts

FieldValue
CompanySolidigm
TitleIP Logic Design Engineer
Normalized title-
Department / teamNAND Development
LocationRancho Cordova, United States
Work model-
Employment typeFull Time
Salary$105,440–$164,800 / year
Statusactive
ATS providerSmartRecruiters
Posted / first seen2026-01-23 / 2026-05-31
Changed / last seen2026-05-31 / 2026-06-04

Related slices

PageWhat it containsOpen
Company jobsActive postings from Solidigm.Open
Company breakdownsRole, location, ATS, and work model facets for this company.Open
ATS provider jobsActive postings observed through SmartRecruiters.Open
Provider filtered searchThe same provider as a filtered job collection.Open
City jobsActive postings in Rancho Cordova.Open
Department jobsActive postings in NAND Development.Open
Lifecycle eventsOpen, update, close, and reopen events for this posting.Open
Original postingCanonical source or apply URL captured from the ATS.Open

Linked records

CompanySolidigm
Sourced2d76f72-69cc-40d9-8c6f-d41778e65e1a
ATS providerSmartRecruiters

Description

Join a multibillion-dollar global company that brings together amazing technology, people, and operational scale to become a powerhouse in the memory industry. Headquartered in Rancho Cordova, California, Solidigm combines elements of an established, successful technology company with the spirit, agility, and entrepreneurial mindset of a start-up. In addition to the U.S. headquarters and other facilities in the U.S., the company has international presence in Asia, Europe, and the Americas. Solidigm will continue to lead the world in innovating new Memory technologies with aspirations to be the #1 NAND memory company in the world. At Solidigm, we view problems as opportunities to define innovative solutions that hold the power to change the world and unleash the potential technological needs that the future holds. At Solidigm, we are One Team that fosters a diverse, equitable, and inclusive culture that embraces individual uniqueness and empowers us to bring our best selves to deliver excellence in support of Solidigm's vision and mission to be the go-to partner for optimized data storage solutions. You can be part of the takeoff of an innovative business that develops cutting-edge products, delivers strong business value for customers, provides an engaging workplace for its employees, and serves a greater impact on the world. This is a golden opportunity for the right applicant to join us and help design, build, and lead Solidigm. We want a diverse team of dedicated professionals who will not just be Solidigm team members but contribute to how we shape the future of the organization. We are seeking applicants who will grow and thrive in our culture; be customer inspired, trusting, innovative, team-oriented, inclusive, results driven, collaborative, passionate, and flexible. Join Solidigm’s visionary Design Engineering Team as a 3D NAND IP Logic Design Engineer and help shape the future of memory technology. Job responsibilities include, but not limited to: Architect, design, and verify logic and circuit blocks for 3D NAND flash memory components Define micro-architecture specifications, implement RTL in SystemVerilog, generate synthesis netlists with appropriate constraints, perform static timing analysis, resolve violations, implement ECOs, and drive design sign-off Develop and optimize microcode-based 3D NAND algorithms (read, program, erase, power-on) using proprietary instruction sets and compilers Contribute to next-gen 3D NAND architecture and pathfinding to improve density, die-size, performance, power, and cost Collaborate with pre-silicon verification teams to build unit-level test benches, implement SystemVerilog Assertions (SVAs), run full-chip RTL and gate-level simulation (GLS) regressions, and ensure functional and code coverage for various read-window-budget and customer features Review pre-silicon analog and mixed signal (AMS) simulations and post-silicon microprobe waveforms to conduct power & performance modeling and ensure the functionality of various digital & analog blocks Partner with product engineering and technology development teams to define Read-Window-Budget (RWB) features and develop Design for Testability (DFT) methods that reduce test time and cost while improving quality Support post-silicon debug and failure analysis across multiple configurations MS in electrical or computer engineering with 7+ years of experience, or BS with 9+ years of experience Proven expertise in Verilog and SystemVerilog, with deep understanding of ASIC design flow: RTL design, logic synthesis, STA, ECO Experience with lint tools, CDC/RDC analysis, and timing constraints Strong background in design verification tools and automation scripting Prior experience in 3D NAND Flash Memory logic design is a plus Ability to work independently across pre- and post-silicon debug cycles The compensation range for this role is $105,440 - $164,800. Actual compensation is influenced by a variety of factors including but not limited to skills, experience, qualifications, and geographic location. Powered by SmartRecruiters - Candidate Privacy Policy

Full job record

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Org ID7bbbc5d7-486c-4d83-a5f0-3479839268e0
Source IDd2d76f72-69cc-40d9-8c6f-d41778e65e1a
Board IDd2d76f72-69cc-40d9-8c6f-d41778e65e1a
Providersmartrecruiters
Provider Job Key744000105233665
TitleIP Logic Design Engineer
Normalized Title
Statusactive
Activeyes
Location TextRancho Cordova, , United States
DepartmentNAND Development
Team
Employment Typefull_time
Workplace Type
Remote Policy
CountryUnited States
Region
CityRancho Cordova
Salary RawUSD 105440-164800 year
Salary Min105,440
Salary Max164,800
Salary CurrencyUSD
Salary Periodyear
Source URLhttps://jobs.smartrecruiters.com/Solidigm/744000105233665-ip-logic-design-engineer
Apply URLhttps://jobs.smartrecruiters.com/Solidigm/744000105233665-ip-logic-design-engineer?oga=true
First Seen At2026-05-31 17:44:21Z
Last Seen At2026-06-04 12:10:36Z
Last Checked At2026-06-04 12:10:36Z
Last Changed At2026-05-31 17:44:21Z
Inactive At
Source Posted At2026-01-23 22:52:25Z
Source Updated At
Raw Payload Uris3://bluework-jobs-prod-raw-590183727216/raw/provider=smartrecruiters/board=solidigm/date=2026-06-04/2026-06-04T12-10-32-248Z-ded2632e71548ec1f27f23c13bfd1773d829222d3cb738c7141c07e025cd0c48.json
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