FPGA Design Engineer - Avionics

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  "lists": [
    {
      "text": "Key Responsibilities:",
      "content": "<ul style=\"margin-top: 0in; margin-bottom: 3.0pt;\">\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Design and implement RTL in SystemVerilog or VHDL for satellite avionics FPGAs across a variety of FPGA platforms.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Develop AXI Memory-Mapped and AXI-Stream protocol implementations for inter-subsystem communication.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Perform FPGA resource and size estimation including logic, memory, and DSP budgeting.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Implement clock-domain-crossing (CDC) design techniques and verify timing closure across designs.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Design clock/reset tree architectures and manage timing-closure strategies for complex multi-clock designs.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Develop SPI, I²C, GPIO, and other low-speed peripheral interfaces alongside high-speed transceiver links.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Apply fault-tolerant digital design techniques including TMR, ECC, scrubbing, and SEE mitigation.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Perform synthesis and place-and-route using vendor toolchains, including custom placement constraints.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Support board bring-up by developing configuration, interface verification, and debug test sequences.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Collaborate with digital design, power, and PCB layout engineers to ensure FPGA support circuitry meets requirements.</li>\n</ul>"
    },
    {
      "text": "Required Qualifications:",
      "content": "\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">5+ years of FPGA design experience in aerospace, defense, or high-reliability systems.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Proficiency in SystemVerilog and/or VHDL for RTL design.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Experience with FPGA synthesis, place-and-route, and timing closure workflows.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Demonstrated knowledge of AXI or similar bus protocols and interface design.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Experience with clock-domain crossing techniques, FIFO design, and multi-clock architectures.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Understanding of radiation effects on FPGAs and mitigation strategies (TMR, ECC, scrubbing).</li>\n"
    },
    {
      "text": "Preferred Qualifications:",
      "content": "<ul style=\"margin-top: 0in; margin-bottom: 3.0pt;\">\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Experience with a variety of FPGA platforms and vendor toolchains (e.g., flash-based, SRAM-based, anti-fuse architectures).</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Background in signal processing (FFT, FIR/IIR filters) and DSP integration.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Experience with transceiver design and high-speed serial communications on FPGAs.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Exposure to DAC/ADC interfaces and mixed-signal digital handling.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Experience with satellite or spacecraft FPGA applications.</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Proficiency in Python or TCL scripting for automation and build infrastructure.</li>\n</ul>"
    },
    {
      "text": "Tools & Technologies: ",
      "content": "<ul style=\"margin-top: 0in; margin-bottom: 3.0pt;\">\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">FPGA vendor toolchains (synthesis, place-and-route, timing analysis)</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">RTL simulation tools (e.g., VCS, QuestaSim, or equivalent)</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Python, TCL, or shell scripting for build automation</li>\n<li style=\"margin: 0in 0in 3pt 0px; font-size: 11pt; font-family: Arial, sans-serif;\">Makefiles for FPGA build workflows</li>\n</ul>"
    }
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