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Senior FPGA Design Engineer

F19e6e07 2cdd 41fb 909f 0481e661660a 19000101 000001 · Melbourne, FL, US, Melbourne, FL; Greenville, SC, US, Greenville, SC · Remote · Active · $120,000–$150,000 / year · ADP Workforce Now Recruiting

Job facts

FieldValue
CompanyF19e6e07 2cdd 41fb 909f 0481e661660a 19000101 000001
TitleSenior FPGA Design Engineer
Normalized title-
Department / team-
LocationMelbourne, FL, United States
Work modelRemote / Remote
Employment typeFull Time
Salary$120,000–$150,000 / year
Statusactive
ATS providerADP Workforce Now Recruiting
Posted / first seen2026-03-16 / 2026-05-31
Changed / last seen2026-06-17 / 2026-06-17

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CompanyF19e6e07 2cdd 41fb 909f 0481e661660a 19000101 000001
Source71733ef3-c996-4a6f-b948-7fe34e5286b8
ATS providerADP Workforce Now Recruiting

Description

Job Title: Senior FPGA Engineer Department: Engineering Reports To: Functional Team Lead / Program Manager FLSA Status: Exempt / Full-time Salary Range: $120k - $150k Annually ROLE We are seeking a Senior FPGA Design Engineer with at least 10 years of experience to develop the architecture, implementation, and verification of complex, high-speed FPGA solutions. The ideal candidate will have deep expertise in high-bandwidth interfaces such as PCIe Gen4/5, 10 to 100G+ Ethernet, and DDR4/DDR5, along with strong skills in RTL design (VHDL/Verilog/ SystemVerilog), timing closure, and signal integrity. Experience with Cryptography, DSP and RF applications is strong plus. This role involves driving FPGA design from concept through production, integrating vendor IP, optimizing for low latency and high throughput, and performing rigorous verification and lab validation. The engineer will collaborate across hardware and software teams, mentor junior engineers, and ensure designs meet stringent reliability and compliance standards. RESPONSIBILITIES Lead full life-cycle FPGA development, from requirements and architecture through RTL implementation (Verilog/VHDL), verification, and system integration across multiple FPGA families. Define and document FPGA architecture, including block diagrams, clocking strategies, and trade-off analyses; participate in and conduct design reviews. Develop robust, reusable, and self-checking testbenches; implement functional coverage models and achieve code coverage closure. Create and execute detailed test plans, procedures, and reports; ensure verification rigor and traceability. Collaborate with hardware and software teams to integrate FPGA designs at the board and system level; support lab bring-up, debug, and qualification testing. Implement and validate JTAG boundary scan and other DFT features; ensure compliance with design-for-test and reliability standards. Drive continuous improvement in design practices, coding standards, and verification methodologies; mentor junior engineers and contribute to technical reviews. REQUIRED SKILLS Strong proficiency in RTL design using Verilog/VHDL, including custom implementations beyond vendor IP integration. Strong experience in testbench development, functional coverage, and verification of complex FPGA designs. Proficient with FPGA simulation and synthesis tools (e.g., QuestaSim, ModelSim, Riviera-PRO, Xilinx Vivado, Intel Quartus). Proficiency of FPGA architecture and optimization techniques for timing closure, floor-planning, and resource utilization. Ability to perform FPGA power estimation and analysis using vendor tools and optimize designs for power and thermal constraints. Strong understanding of high-speed interfaces (PCIe, Ethernet, Serial RapidIO, DDRx) and control protocols (I²C, SPI, RS-232/422). Experience with System-on-Chip technologies. PREFERRED SKILLS Proficiency in FPGA Block Design development and debugging (e.g., Vivado, Libero). Familiarity with Universal Verification Methodology (UVM). Familiarity with Microsemi Libero and Lattus Diamond. Familiarity with revision control systems (Git/Bitbucket) and scripting in Python, TCL, or Linux shell for automation. Skilled in FPGA lab validation using oscilloscopes, logic analyzers, and protocol analyzers. Support JTAG Boundary scan design and testing Experience with Cryptography, Digital Signal Processing and RF Applications MATLAB modeling Strong oral and written communication skills, with ability to document and present technical work clearly. Experience collaborating in Agile environments and using tools like Jira and requirements management systems (e.g., Jama). Familiarity with Manufacturing processes, and Electronic Stress Screening. Understanding of formal verification processes and compliance standards. QUALIFICATIONS Bachelor’s Degree in Electrical Engineering, Computer Engineering, or related field. Minimum 10 years of relevant experience in FPGA design. Excellent written and verbal communication skills. Ability to work in a collaborative team environment. US Person required; ability to obtain and maintain a DoD Secret clearance. Position located in Melbourne, FL or Greenville, SC (not remote).

Full job record

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First Seen At2026-05-31 18:36:34Z
Last Seen At2026-06-17 13:40:22Z
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The ideal candidate will have deep expertise in high-bandwidth interfaces such as PCIe Gen4/5, 10 to 100G+ Ethernet, and DDR4/DDR5, along with strong skills in RTL design (VHDL/Verilog/ SystemVerilog), timing closure, and signal integrity. Experience with Cryptography, DSP and RF applications is strong plus. This role involves driving FPGA design from concept through production, integrating vendor IP, optimizing for low latency and high throughput, and performing rigorous verification and lab validation. The engineer will collaborate across hardware and software teams, mentor junior engineers, and ensure designs meet stringent reliability and compliance standards.</span></p><p style='margin-top:0in;margin-right:0in;margin-bottom:8.0pt;margin-left:0in;font-size:11.0pt;font-family:\"Calibri\",sans-serif;line-height:normal;'><span style='font-family: \"times new roman\", serif; font-size: 18px;'><strong>RESPONSIBILITIES</strong></span></p><div style='margin-top:0in;margin-right:0in;margin-bottom:8.0pt;margin-left:0in;font-size:11.0pt;font-family:\"Calibri\",sans-serif;'><ul style=\"margin-bottom:0in;list-style-type: disc;\"><li style='margin: 0in 0in 8pt; font-size: 18px; font-family: \"times new roman\", serif;'>Lead full life-cycle FPGA development, from requirements and architecture through RTL implementation (Verilog/VHDL), verification, and system integration across multiple FPGA families.&nbsp;</li><li style='margin: 0in 0in 8pt; font-size: 18px; font-family: \"times new roman\", serif;'>Define and document FPGA architecture, including block diagrams, clocking strategies, and trade-off analyses; participate in and conduct design reviews.&nbsp;</li><li style='margin: 0in 0in 8pt; font-size: 18px; font-family: \"times new roman\", serif;'>Develop robust, reusable, and self-checking testbenches; implement functional coverage models and achieve code coverage closure.&nbsp;</li><li style='margin: 0in 0in 8pt; font-size: 18px; font-family: \"times new roman\", serif;'>Create and execute detailed test plans, procedures, and reports; ensure verification rigor and traceability.&nbsp;</li><li style='margin: 0in 0in 8pt; font-size: 18px; font-family: \"times new roman\", serif;'>Collaborate with hardware and software teams to integrate FPGA designs at the board and system level; support lab bring-up, debug, and qualification testing.&nbsp;</li><li style='margin: 0in 0in 8pt; font-size: 18px; font-family: \"times new roman\", serif;'>Implement and validate JTAG boundary scan and other DFT features; ensure compliance with design-for-test and reliability standards.&nbsp;</li><li style='margin: 0in 0in 8pt; font-size: 18px; font-family: \"times new roman\", serif;'>Drive continuous improvement in design practices, coding standards, and verification methodologies; mentor junior engineers and contribute to technical reviews.</li></ul></div><p style='margin-top:0in;margin-right:0in;margin-bottom:8.0pt;margin-left:0in;font-size:11.0pt;font-family:\"Calibri\",sans-serif;line-height:normal;'><span style='font-family: \"times new roman\", serif; font-size: 18px;'><strong>REQUIRED SKILLS</strong></span></p><div style='margin-top:0in;margin-right:0in;margin-bottom:8.0pt;margin-left:0in;font-size:11.0pt;font-family:\"Calibri\",sans-serif;'><ul style=\"margin-bottom:0in;list-style-type: disc;\"><li style='margin: 0in 0in 8pt; font-size: 18px; font-family: \"times new roman\", serif;'>Strong proficiency in RTL design using Verilog/VHDL, including custom implementations beyond vendor IP integration.</li><li style='margin: 0in 0in 8pt; font-size: 18px; font-family: \"times new roman\", serif;'>Strong experience in testbench development, functional coverage, and verification of complex FPGA designs.&nbsp;</li><li style='margin: 0in 0in 8pt; font-size: 18px; font-family: \"times new roman\", serif;'>Proficient with FPGA simulation and synthesis tools (e.g., QuestaSim, ModelSim, Riviera-PRO, Xilinx Vivado, Intel Quartus).</li><li style='margin: 0in 0in 8pt; font-size: 18px; font-family: \"times new roman\", serif;'>Proficiency of FPGA architecture and optimization techniques for timing closure, floor-planning, and resource utilization.</li><li style='margin: 0in 0in 8pt; font-size: 18px; font-family: \"times new roman\", serif;'>Ability to perform FPGA power estimation and analysis using vendor tools and optimize designs for power and thermal constraints.</li><li style='margin: 0in 0in 8pt; font-size: 18px; font-family: \"times new roman\", serif;'>Strong understanding of high-speed interfaces (PCIe, Ethernet, Serial RapidIO, DDRx) and control protocols (I&sup2;C, SPI, RS-232/422).&nbsp;</li><li style='margin: 0in 0in 8pt; font-size: 18px; font-family: \"times new roman\", serif;'>Experience with System-on-Chip technologies.</li></ul></div><p style='margin-top:0in;margin-right:0in;margin-bottom:0in;margin-left:0in;font-size:11.0pt;font-family:\"Calibri\",sans-serif;line-height:15.0pt;'><span style='font-size: 18px; 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font-size: 18px; font-family: \"times new roman\", serif;'>Familiarity with revision control systems (Git/Bitbucket) and scripting in Python, TCL, or Linux shell for automation.&nbsp;</li><li style='margin: 0in 0in 8pt; font-size: 18px; font-family: \"times new roman\", serif;'>Skilled in FPGA lab validation using oscilloscopes, logic analyzers, and protocol analyzers.&nbsp;</li><li style='margin: 0in 0in 8pt; font-size: 18px; font-family: \"times new roman\", serif;'><span style=\"line-height: 107%;\">Support JTAG Boundary scan design and testing</span></li><li style='margin: 0in 0in 8pt; font-size: 18px; font-family: \"times new roman\", serif;'><span style=\"line-height: 107%;\">Experience with Cryptography, Digital Signal Processing and RF Applications</span></li><li style='margin: 0in 0in 8pt; font-size: 18px; font-family: \"times new roman\", serif;'><span style=\"line-height: 107%;\">MATLAB modeling</span></li><li style='margin: 0in 0in 8pt; font-size: 18px; font-family: \"times new roman\", serif;'>Strong oral and written communication skills, with ability to document and present technical work clearly.&nbsp;</li></ul></div><ul type=\"disc\" style=\"margin-bottom:0in;\"><li style='margin: 0in 0in 8pt; font-size: 18px; font-family: \"times new roman\", serif; line-height: normal;'>Experience collaborating in Agile environments and using tools like Jira and requirements management systems (e.g., Jama).</li><li style='margin: 0in 0in 8pt; font-size: 18px; font-family: \"times new roman\", serif; line-height: normal;'>Familiarity with Manufacturing&nbsp;processes, and Electronic Stress Screening.</li><li style='margin: 0in 0in 8pt; font-size: 18px; font-family: \"times new roman\", serif; line-height: normal;'>Understanding of formal verification processes and compliance standards.</li></ul><p style='margin-top:0in;margin-right:0in;margin-bottom:8.0pt;margin-left:0in;font-size:11.0pt;font-family:\"Calibri\",sans-serif;line-height:normal;'><span style='font-family: \"times new roman\", serif; font-size: 18px;'><strong>QUALIFICATIONS</strong></span></p><ul type=\"disc\" style=\"margin-bottom:0in;\"><li style='margin: 0in 0in 8pt; font-size: 18px; font-family: \"times new roman\", serif; line-height: normal;'>Bachelor&rsquo;s Degree in Electrical Engineering, Computer Engineering, or related field.</li><li style='margin: 0in 0in 8pt; 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