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Substrate Layout Design Engineer

Eridu · Saratoga, CA, United States · On Site · Active · $240,000–$275,000 / year · Rippling ATS

Job facts

FieldValue
CompanyEridu
TitleSubstrate Layout Design Engineer
Normalized title-
Department / teamSystems Engineering
LocationSaratoga, CA, United States
Work modelOn Site
Employment typeFull Time
Salary$240,000–$275,000 / year
Statusactive
ATS providerRippling ATS
Posted / first seen2026-05-01 / 2026-05-29
Changed / last seen2026-06-06 / 2026-06-06

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Linked records

CompanyEridu
Source2e3b3faf-1f18-443b-b03c-ab436c316a6b
ATS providerRippling ATS

Description

company About Eridu Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI . Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability. The company’s solutions and value proposition have been widely validated by leading hyperscalers. Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu is working with best-in-class supply chain partners including silicon, packaging and systems. Visit our website eridu.ai to learn more. role Position Overview We are seeking an experienced Substrate Layout Design Engineer to support the development of an advanced multi-die organic based flip chip module that integrates multiple dies in a chiplet format within a high-density, high-performance substrate. This role focuses on physical layout of the substrate using Siemens Xpedition tool, routing feasibility, and co-design alignment with floor planning, mechanical, and system constraints. Additionally, design of organic based substrates for SMT attachment with multilayer ABF based stack up. The successful candidate will collaborate closely with package integration, signal/power integrity, and system mechanical teams to ensure successful layout implementation and manufacturability for a complex multi-chip package. Responsibilities Drive physical layout of high-density substrate designs for advanced multi-die packages, including planning of bump maps, netlist alignments, escape/breakout routing, via structures, and layer stack-up definition for optimum performance of signal and power connectivity. Assess routing feasibility in a co-design environment, considering die floorplans, netlist, IO bump placement, and mechanical constraints at both the component and system levels. Collaborate with system architects, packaging engineers, ASIC, SI/PI, and mechanical teams to align on floor planning strategies and package mechanical outline and structure. Optimize signal, power, and ground integrity through intelligent routing, layer usage, and design constraint enforcement. Execute DRC, DFM, and manufacturing rule checks to ensure design readiness for fabrication and assembly. Generate and release final design packages and interface with substrate vendors for fabrication and manufacturability. Support technical reviews of substrate layouts and iterate with internal and external stakeholders on design improvements for optimum performance. Qualifications 8+ years of experience in advanced substrate layout for high-performance IC packaging, with direct involvement in multi-die or chiplet-based designs. Proven expertise in organic substrate layout with high routing density, fine-pitch bump escape, and constrained layer stack-ups. Experience in PCB design layout and schematic. Strong understanding of co-design methodology, including interactions between floorplan, substrate layout, and system mechanical boundaries. Proficient with Siemens Xpedition, Allegro Cadence APD, design tools. Familiarity with SI/PI design principles and how organic substrate layout impacts electrical performance. Experienced in working with OSATs or substrate suppliers for design tape-out and manufacturability validation. Familiarity with substrate design rules and materials, substrate manufacturing. Excellent communication and documentation skills. Bachelor or Master degree in Electrical, Mechanical, or Packaging Engineering, or equivalent. Why Join Us? At Eridu, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers. The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles. Notice to Recruiting Agencies Eridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted to Eridu without prior written authorization from our recruiting team will be considered unsolicited and will become the property of Eridu. Eridu reserves the right to pursue and hire such candidates without any obligation to pay fees. Recruiting agencies are expressly instructed not to contact hiring managers, employees, or executives regarding open positions.

Full job record

Job ID0335fec136a2789e87f8f9d41bc67bf5df4ad05d
Org IDd05d9cdc-fa71-444b-b57a-6140fe525606
Source ID2e3b3faf-1f18-443b-b03c-ab436c316a6b
Board ID2e3b3faf-1f18-443b-b03c-ab436c316a6b
Providerrippling
Provider Job Key4b8364db-5acb-4e02-90f3-25d4387098fe
TitleSubstrate Layout Design Engineer
Normalized Title—
Statusactive
Activeyes
Location TextSaratoga, CA, United States
DepartmentSystems Engineering
Team—
Employment Typefull_time
Workplace Typeon_site
Remote Policy—
CountryUnited States
RegionCA
CitySaratoga
Salary RawUSD 240000-275000 YEAR
Salary Min240,000
Salary Max275,000
Salary CurrencyUSD
Salary Periodyear
Source URLhttps://ats.rippling.com/eridu-ai/jobs/4b8364db-5acb-4e02-90f3-25d4387098fe
Apply URLhttps://ats.rippling.com/eridu-ai/jobs/4b8364db-5acb-4e02-90f3-25d4387098fe
First Seen At2026-05-29 07:14:02Z
Last Seen At2026-06-06 19:44:35Z
Last Checked At2026-06-06 19:44:35Z
Last Changed At2026-06-06 19:44:35Z
Inactive At—
Source Posted At2026-05-01 00:55:36Z
Source Updated At—
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      "role": "<meta><h4 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:18pt;font-weight:600;letter-spacing:0px;margin-top:12px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"white-space:pre-wrap;\">Position Overview</strong></b></h4><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"white-space:pre-wrap;\">We are seeking an experienced&nbsp;Substrate Layout Design Engineer&nbsp;to support the development of an advanced multi-die organic based flip chip module that integrates multiple dies in a chiplet format within a high-density, high-performance substrate. This role focuses on physical layout of the substrate using Siemens Xpedition tool, routing feasibility, and co-design alignment with floor planning, mechanical, and system constraints.</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><br></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"white-space:pre-wrap;\">Additionally, design of organic based substrates for SMT attachment with multilayer ABF based stack up.</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><br></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"white-space:pre-wrap;\">The successful candidate will collaborate closely with package integration, signal/power integrity, and system mechanical teams to ensure successful layout implementation and manufacturability for a complex multi-chip package.</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><br></p><h4 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:18pt;font-weight:600;letter-spacing:0px;margin-top:12px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"white-space:pre-wrap;\">Responsibilities&nbsp;</strong></b></h4><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Drive physical layout of high-density substrate designs for advanced multi-die packages, including planning of bump maps, netlist alignments, escape/breakout routing, via structures, and layer stack-up definition for optimum performance of signal and power connectivity.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Assess&nbsp;routing feasibility in a co-design environment, considering die floorplans, netlist, IO bump placement, and mechanical constraints at both the component and system levels.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Collaborate with system architects, packaging engineers, ASIC, SI/PI, and mechanical teams to align on floor planning strategies and package mechanical outline and structure.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Optimize signal, power, and ground integrity through intelligent routing, layer usage, and design constraint enforcement.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Execute DRC, DFM, and manufacturing rule checks to ensure design readiness for fabrication and assembly.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Generate and release final design packages and interface with substrate vendors for fabrication and manufacturability.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Support technical reviews of substrate layouts and iterate with internal and external stakeholders on design improvements for optimum performance.</span></li></ul><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><br></p><h4 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:18pt;font-weight:600;letter-spacing:0px;margin-top:12px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"white-space:pre-wrap;\">Qualifications</strong></b></h4><ul data-pattern=\"discCircleSquare\" data-depth=\"1\" style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;margin:8px 0px;line-height:1.6;padding:0px 0px 0px 32px;list-style-type:disc;\"><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">8+ years of experience in advanced substrate layout for high-performance IC packaging, with direct involvement in multi-die or chiplet-based designs.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Proven expertise in organic substrate layout with high routing density, fine-pitch bump escape, and constrained layer stack-ups.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Experience in PCB design layout and schematic.&nbsp;</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Strong understanding of&nbsp;co-design methodology, including interactions between floorplan, substrate layout, and system mechanical boundaries.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Proficient with Siemens Xpedition,&nbsp; Allegro Cadence APD, design tools.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Familiarity with SI/PI design principles and how organic substrate layout impacts electrical performance.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Experienced in working with OSATs or substrate suppliers for design tape-out and manufacturability validation.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Familiarity with substrate design rules and materials, substrate manufacturing.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Excellent communication and documentation skills.</span></li><li style=\"font-size:11pt;margin:3px 0px;letter-spacing:0.25px;line-height:1.6;\"><span style=\"white-space:pre-wrap;\">Bachelor or Master degree in Electrical, Mechanical, or Packaging Engineering, or equivalent.</span></li></ul><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;text-align:start;\"><br></p><h4 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:18pt;font-weight:600;letter-spacing:0px;margin-top:12px;margin-bottom:4px;text-align:start;padding-left:0px;\"><b><strong style=\"color:black;white-space:pre-wrap;\">Why Join Us?&nbsp;</strong></b></h4><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"color:black;font-size:11pt;white-space:pre-wrap;\">At Eridu, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.&nbsp;</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"color:black;font-size:11pt;white-space:pre-wrap;\">&nbsp;</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"color:black;font-size:11pt;white-space:pre-wrap;\">The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.&nbsp;</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;text-align:start;\"><br></p><h6 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:13pt;font-weight:600;letter-spacing:0.25px;margin-top:8px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"white-space:pre-wrap;\">Notice to Recruiting Agencies</strong></b></h6><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Eridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted to Eridu without prior written authorization from our recruiting team will be considered unsolicited and will become the property of Eridu. Eridu reserves the right to pursue and hire such candidates without any obligation to pay fees. Recruiting agencies are expressly instructed not to contact hiring managers, employees, or executives regarding open positions.</span></p>",
      "company": "<meta><h4 style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;line-height:1.6;font-size:18pt;font-weight:600;letter-spacing:0px;margin-top:12px;margin-bottom:4px;padding-left:0px;\"><b><strong style=\"white-space:pre-wrap;\">About Eridu</strong></b></h4><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver </span><i><em style=\"font-size:11pt;white-space:pre-wrap;\">Faster AI</em></i><span style=\"font-size:11pt;white-space:pre-wrap;\">. Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability.</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">&nbsp;</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">The company’s solutions and value proposition have been widely validated by leading hyperscalers.</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">&nbsp;</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu is working with best-in-class supply chain partners including silicon, packaging and systems.</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">&nbsp;</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">Visit our website </span><a href=\"http://eridu.ai\" target=\"_blank\" class=\"css-173makr-linkStyle\" style=\"color:rgb(30,74,169);cursor:pointer;\"><span style=\"font-size:11pt;white-space:pre-wrap;\">eridu.ai</span></a><span style=\"font-size:11pt;white-space:pre-wrap;\"> to learn more.</span></p><p style=\"font-family:&quot;Basel Grotesk&quot;,Arial,sans-serif;font-size:11.25pt;font-weight:400;line-height:1.6;letter-spacing:0.25px;margin:4px 0px;padding:0px;text-align:left;\"><br></p>"
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GET https://api.bluedoor.sh/job-postings/v1/jobs/0335fec136a2789e87f8f9d41bc67bf5df4ad05d?include=descriptionJSON
GET https://api.bluedoor.sh/job-postings/v1/orgs/d05d9cdc-fa71-444b-b57a-6140fe525606JSON
GET https://api.bluedoor.sh/job-postings/v1/sources/2e3b3faf-1f18-443b-b03c-ab436c316a6bJSON
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