Technology Lead- Memory Layout

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      "Value": "<span style=\"font-size:14px;\"><span style=\"font-family:Arial,Helvetica,sans-serif;\">Infosys is hiring Memory Team Layout. You will work along our Registers and Memory Arrays and Memory data path layout and design engineers .Based on the schematic shared you should be able to take it forward and collaborate with circuit team etc to create best layout possible.<br><br>Required Qualifications:</span></span><ul><li><span style=\"font-size:14px;\"><span style=\"font-family:Arial,Helvetica,sans-serif;\">Candidate must be located within commuting distance of </span></span>Vancouver&nbsp;<span style=\"font-size:14px;\"><span style=\"font-family:Arial,Helvetica,sans-serif;\">BC, Canada or be willing to relocate to the area. This position may require travel in Canada.</span></span></li><li><span style=\"font-size:14px;\"><span style=\"font-family:Arial,Helvetica,sans-serif;\">Bachelor’s degree or foreign equivalent required from an accredited institution. Will also consider three years of progressive experience in the specialty in lieu of every year of education.</span></span></li><li><span style=\"font-size:14px;\"><span style=\"font-family:Arial,Helvetica,sans-serif;\">At least 4 years of Information Technology experience.</span></span></li><li><span style=\"font-size:14px;\"><span style=\"font-family:Arial,Helvetica,sans-serif;\">Candidates authorized to work for any employer in the Canada without employer-based visa sponsorship are welcome to apply. Infosys is unable to provide immigration sponsorship for this role at this time.</span></span></li></ul><span style=\"font-size:14px;\"><span style=\"font-family:Arial,Helvetica,sans-serif;\">Required Skills</span></span><ul><li><span style=\"font-size:14px;\"><span style=\"font-family:Arial,Helvetica,sans-serif;\">Minimum Qualifications 5+ years of experience in Compiler/Custom Memory Layout design. </span></span></li><li><span style=\"font-size:14px;\"><span style=\"font-family:Arial,Helvetica,sans-serif;\">Memory Leafcell layout library design from scratch including top level integration. </span></span></li><li><span style=\"font-size:14px;\"><span style=\"font-family:Arial,Helvetica,sans-serif;\">Good knowledge on diAerent types of memory architectures. </span></span></li><li><span style=\"font-size:14px;\"><span style=\"font-family:Arial,Helvetica,sans-serif;\">Good knowledge in optimized layout design for better performance. </span></span></li><li><span style=\"font-size:14px;\"><span style=\"font-family:Arial,Helvetica,sans-serif;\">Sound knowledge &amp; hands on experience in Finfet technology, layout design and DRC limitations.</span></span></li><li><span style=\"font-size:14px;\"><span style=\"font-family:Arial,Helvetica,sans-serif;\">3nm, 5 nm exposure required Proficient in physical verification flow &amp; debug, like DRC, LVS, ERC, Boundary conditions. </span></span></li><li><span style=\"font-size:14px;\"><span style=\"font-family:Arial,Helvetica,sans-serif;\">Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow.</span></span></li></ul><span style=\"font-size:14px;\"><span style=\"font-family:Arial,Helvetica,sans-serif;\">The job may also entail sitting as well as working at a computer for extended periods of time. &nbsp;Candidates should be able to effectively communicate by telephone, email, and face to face.<br><br>Estimated annual compensation range for the candidate based in the below location will be:<br>BC- $90450 to&nbsp; $136500&nbsp;</span></span>",
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